coriolis/hurricane/src/isobar/PyHorizontal.cpp

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// -*- C++ -*-
//
// This file is part of the Coriolis Software.
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// Copyright (c) UPMC 2007-2016, All Rights Reserved
//
// +-----------------------------------------------------------------+
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// | C O R I O L I S |
// | I s o b a r - Hurricane / Python Interface |
// | |
// | Author : Sophie BELLOEIL |
// | E-mail : Jean-Paul.Chaput@lip6.fr |
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// | =============================================================== |
// | C++ Module : "./PyHorizontal.cpp" |
// +-----------------------------------------------------------------+
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#include "hurricane/isobar/PyNet.h"
#include "hurricane/isobar/PyLayer.h"
#include "hurricane/isobar/PyHorizontal.h"
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namespace Isobar {
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using namespace Hurricane;
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extern "C" {
# undef ACCESS_OBJECT
# undef ACCESS_CLASS
# define ACCESS_OBJECT _baseObject._baseObject._baseObject._object
# define ACCESS_CLASS(_pyObject) &(_pyObject->_baseObject._baseObject._baseObject)
# define METHOD_HEAD(function) GENERIC_METHOD_HEAD(Horizontal,horizontal,function)
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// x=================================================================x
// | "PyHorizontal" Python Module Code Part |
// x=================================================================x
# if defined(__PYTHON_MODULE__)
// x-------------------------------------------------------------x
// | "PyHorizontal" Attribute Methods |
// x-------------------------------------------------------------x
DirectGetLongAttribute(PyHorizontal_getY ,getY ,PyHorizontal,Horizontal)
DirectGetLongAttribute(PyHorizontal_getDxSource,getDxSource,PyHorizontal,Horizontal)
DirectGetLongAttribute(PyHorizontal_getDxTarget,getDxTarget,PyHorizontal,Horizontal)
DirectSetLongAttribute(PyHorizontal_setY ,setY ,PyHorizontal,Horizontal)
DirectSetLongAttribute(PyHorizontal_setDxSource,setDxSource,PyHorizontal,Horizontal)
DirectSetLongAttribute(PyHorizontal_setDxTarget,setDxTarget,PyHorizontal,Horizontal)
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// Standart destroy (Attribute).
DBoDestroyAttribute(PyHorizontal_destroy, PyHorizontal)
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// ---------------------------------------------------------------
// Attribute Method : "PyHorizontal_create ()"
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static PyObject* PyHorizontal_create ( PyObject*, PyObject *args ) {
cdebug.log(20) << "PyHorizontal_create()" << endl;
PyObject* arg0;
PyObject* arg1;
PyObject* arg2;
PyObject* arg3;
PyObject* arg4;
PyObject* arg5;
PyObject* arg6;
Horizontal* horizontal = NULL;
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HTRY
__cs.init ("Horizontal.create");
if ( ! PyArg_ParseTuple(args,"O&O&O&|O&O&O&O&:Horizontal.create"
,Converter,&arg0
,Converter,&arg1
,Converter,&arg2
,Converter,&arg3
,Converter,&arg4
,Converter,&arg5
,Converter,&arg6
)) {
PyErr_SetString ( ConstructorError, "invalid number of parameters for Horizontal constructor." );
return NULL;
}
if ( __cs.getObjectIds() == NET_LAYER_INT_ARG )
horizontal = Horizontal::create ( PYNET_O(arg0)
, PYLAYER_O(arg1)
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
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, PyAny_AsLong(arg2) );
else if ( __cs.getObjectIds() == NET_LAYER_INTS2_ARG )
horizontal = Horizontal::create ( PYNET_O(arg0)
, PYLAYER_O(arg1)
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
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, PyAny_AsLong(arg2)
, PyAny_AsLong(arg3) );
else if ( __cs.getObjectIds() == COMPS2_LAYER_INT_ARG )
horizontal = Horizontal::create ( ComponentCast(arg0)
, ComponentCast(arg1)
, PYLAYER_O(arg2)
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
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, PyAny_AsLong(arg3) );
else if ( __cs.getObjectIds() == NET_LAYER_INTS3_ARG )
horizontal = Horizontal::create ( PYNET_O(arg0)
, PYLAYER_O(arg1)
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
2014-09-13 10:45:30 -05:00
, PyAny_AsLong(arg2)
, PyAny_AsLong(arg3)
, PyAny_AsLong(arg4) );
else if ( __cs.getObjectIds() == COMPS2_LAYER_INTS2_ARG )
horizontal = Horizontal::create ( ComponentCast(arg0)
, ComponentCast(arg1)
, PYLAYER_O(arg2)
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
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, PyAny_AsLong(arg3)
, PyAny_AsLong(arg4) );
else if ( __cs.getObjectIds() == NET_LAYER_INTS4_ARG )
horizontal = Horizontal::create ( PYNET_O(arg0)
, PYLAYER_O(arg1)
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
2014-09-13 10:45:30 -05:00
, PyAny_AsLong(arg2)
, PyAny_AsLong(arg3)
, PyAny_AsLong(arg4)
, PyAny_AsLong(arg5) );
else if ( __cs.getObjectIds() == COMPS2_LAYER_INTS3_ARG )
horizontal = Horizontal::create ( ComponentCast(arg0)
, ComponentCast(arg1)
, PYLAYER_O(arg2)
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
2014-09-13 10:45:30 -05:00
, PyAny_AsLong(arg3)
, PyAny_AsLong(arg4)
, PyAny_AsLong(arg5) );
else if ( __cs.getObjectIds() == COMPS2_LAYER_INTS4_ARG )
horizontal = Horizontal::create ( ComponentCast(arg0)
, ComponentCast(arg1)
, PYLAYER_O(arg2)
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
2014-09-13 10:45:30 -05:00
, PyAny_AsLong(arg3)
, PyAny_AsLong(arg4)
, PyAny_AsLong(arg5)
, PyAny_AsLong(arg6) );
else {
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PyErr_SetString ( ConstructorError, "invalid number of parameters for Horizontal constructor." );
return NULL;
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}
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HCATCH
return PyHorizontal_Link ( horizontal );
}
// ---------------------------------------------------------------
// Attribute Method : "PyHorizontal_translate ()"
static PyObject* PyHorizontal_translate ( PyHorizontal *self, PyObject* args ) {
cdebug.log(20) << "PyHorizontal_translate ()" << endl;
HTRY
METHOD_HEAD ( "Horizontal.translate()" )
DbU::Unit dx=0, dy=0;
if (PyArg_ParseTuple(args,"ll:Horizontal.translate", &dx, &dy)) {
horizontal->translate(dx, dy);
} else {
PyErr_SetString ( ConstructorError, "invalid number of parameters for Horizontal.translate()" );
return NULL;
}
HCATCH
Py_RETURN_NONE;
}
// ---------------------------------------------------------------
// PyHorizontal Attribute Method table.
PyMethodDef PyHorizontal_Methods[] =
{ { "create" , (PyCFunction)PyHorizontal_create , METH_VARARGS|METH_STATIC
, "Create a new Horizontal." }
, { "getY" , (PyCFunction)PyHorizontal_getY , METH_NOARGS , "Get the segment Y position." }
, { "getDxSource", (PyCFunction)PyHorizontal_getDxSource, METH_NOARGS , "Get the segment source X offset." }
, { "getDxTarget", (PyCFunction)PyHorizontal_getDxTarget, METH_NOARGS , "Get the segment target X offset." }
, { "setY" , (PyCFunction)PyHorizontal_setY , METH_VARARGS, "Modify the segment Y position." }
, { "setDxSource", (PyCFunction)PyHorizontal_setDxSource, METH_VARARGS, "Modify the segment source X offset." }
, { "setDxTarget", (PyCFunction)PyHorizontal_setDxTarget, METH_VARARGS, "Modify the segment target X offset." }
, { "translate" , (PyCFunction)PyHorizontal_translate , METH_VARARGS, "Translates the Horizontal segment of dx and dy." }
, { "destroy" , (PyCFunction)PyHorizontal_destroy , METH_NOARGS
, "destroy associated hurricane object, the python object remains." }
, {NULL, NULL, 0, NULL} /* sentinel */
};
// x-------------------------------------------------------------x
// | "PyHorizontal" Object Methods |
// x-------------------------------------------------------------x
DBoDeleteMethod(Horizontal)
PyTypeObjectLinkPyType(Horizontal)
#else // End of Python Module Code Part.
// x=================================================================x
// | "PyHorizontal" Shared Library Code Part |
// x=================================================================x
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// Link/Creation Method.
DBoLinkCreateMethod(Horizontal)
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// ---------------------------------------------------------------
// PyHorizontal Object Definitions.
PyTypeInheritedObjectDefinitions(Horizontal, Segment)
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#endif // End of Shared Library Code Part.
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} // End of extern "C".
} // End of Isobar namespace.