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Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
2018-10-18 11:10:01 -05:00
<!-- Generated by Doxygen 1.8.14 -->
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<div class="title">AGDS Format </div> </div>
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<div class="contents">
<div class="textblock"><h1><a class="anchor" id="agdsPres"></a>
Presentation</h1>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>The <b>Ascii Graphic Database System (AGDS)</b> format is an ascii (text) version of the wellknown and industry standard GDS II binary format. This format hierarchicaly represents geometric shapes, labels and other layout informations (see <a href="http://en.wikipedia.org/wiki/GDSII">http://en.wikipedia.org/wiki/GDSII</a> for more informations). <br />
The ascii format has several advantages versus binary format:</p><ul>
<li>human readable,</li>
<li>easy to edit manually or with dedicated tools,</li>
<li>easy to search or grep into,</li>
<li>easy to compare and understand differences between two files,</li>
<li>easy to convert.</li>
</ul>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>The conversion from Ascii GDS to binary GDS and vice versa can be done with <b>OwlVision GDSII Viewer</b> available at <a href="http://owlvision.org">http://owlvision.org</a><br />
Since it has been developped in java, it can be run on all platforms.</p>
<h2><a class="anchor" id="agdsAutrhos"></a>
Author</h2>
<p>Damien Dupuis: damien.dupuis(at)lip6(.)fr</p>
<h2><a class="anchor" id="agdsLimits"></a>
Limitations</h2>
<p>Currently the only supported shape in this driver is the rectangle.</p>
<h1><a class="anchor" id="agdsDB"></a>
Stand alone database structure</h1>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>The database conists in for simple objects :</p><ul>
<li><a class="el" href="class_a_g_d_s_1_1_library.html">AGDS::Library</a> contains all AGDS library informations such as the name, the units used (user and physical) and the list of all Structures.</li>
<li><a class="el" href="class_a_g_d_s_1_1_structure.html">AGDS::Structure</a> describes a GDS Structure with a name and a list of Elements.</li>
<li><a class="el" href="class_a_g_d_s_1_1_element.html">AGDS::Element</a> is an abstract class from which derived the <a class="el" href="class_a_g_d_s_1_1_rectangle.html">AGDS::Rectangle</a>.</li>
<li><a class="el" href="class_a_g_d_s_1_1_rectangle.html">AGDS::Rectangle</a> describes a rectangle element of a structure.</li>
</ul>
<h2><a class="anchor" id="agdsDriver"></a>
Using the driver</h2>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>To drive an AGDS file, user has to create one <a class="el" href="class_a_g_d_s_1_1_library.html">AGDS::Library</a> and add <a class="el" href="class_a_g_d_s_1_1_structure.html">AGDS::Structure</a> objects to it with the <a class="el" href="class_a_g_d_s_1_1_library.html#a93d333a20154e0b688ff3ff213039171" title="adds a Structure to the Library. ">AGDS::Library::addStructure()</a> method. Each <a class="el" href="class_a_g_d_s_1_1_structure.html">AGDS::Structure</a> contains at least one <a class="el" href="class_a_g_d_s_1_1_element.html">AGDS::Element</a> added with <a class="el" href="class_a_g_d_s_1_1_structure.html#a2dd203e6770f7d15d6f706867c919a60" title="adds an Element to the Structure. ">AGDS::Structure::addElement()</a> method.<br />
All objects can be independently created as far as they are correctly added to their parent. <br />
Once the library is completely specified, simply call the <a class="el" href="class_a_g_d_s_1_1_library.html#a33b9d989b84857f46034085664ff3fa2" title="writes the database to file. ">AGDS::Library::writeToFile()</a> method to drive the database to file.</p>
<h1><a class="anchor" id="agdsExamples"></a>
Examples</h1>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>As said is the global presentation, VLSI SAPD project provides C++ libraries and Python modules for each supported format. In this section we present two simple code examples to drive a AGDS file using C++ or Python. These two examples drive the same file <code>transistor.agds:</code> </p><div class="fragment"><div class="line">HEADER 5;</div><div class="line">BGNLIB;</div><div class="line"> LASTMOD {10-06-11 14:02:15};</div><div class="line"> LASTACC {10-06-11 14:02:15};</div><div class="line">LIBNAME myTestLib.DB;</div><div class="line">UNITS;</div><div class="line"> USERUNITS 0.001;</div><div class="line"> PHYSUNITS 1.000000e-09;</div><div class="line"></div><div class="line">BGNSTR;</div><div class="line"> CREATION {10-06-11 14:02:15};</div><div class="line"> LASTMOD {10-06-11 14:02:15};</div><div class="line">STRNAME Transistor;</div><div class="line"></div><div class="line">BOUNDARY;</div><div class="line">LAYER 17;</div><div class="line">DATATYPE 0;</div><div class="line">XY 5;</div><div class="line"> X: 305; Y: 150;</div><div class="line"> X: 305; Y: 830;</div><div class="line"> X: 365; Y: 830;</div><div class="line"> X: 365; Y: 150;</div><div class="line"> X: 305; Y: 150;</div><div class="line">ENDEL;</div><div class="line"></div><div class="line">BOUNDARY;</div><div class="line">LAYER 6;</div><div class="line">DATATYPE 0;</div><div class="line">XY 5;</div><div class="line"> X: 130; Y: 290;</div><div class="line"> X: 130; Y: 690;</div><div class="line"> X: 540; Y: 690;</div><div class="line"> X: 540; Y: 290;</div><div class="line"> X: 130; Y: 290;</div><div class="line">ENDEL;</div><div class="line"></div><div class="line">ENDSTR;</div><div class="line">ENDLIB;</div></div><!-- fragment --><div class="image">
<img src="transistorCif.png" alt="transistorCif.png"/>
<div class="caption">
AGDS example layout</div></div>
<h2><a class="anchor" id="agdsC"></a>
C++</h2>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
2018-10-18 11:10:01 -05:00
<p>Here is the C++ code (<code>driveAgds.cpp</code>) used to generate the transistor.agds file. (Source is available in examples directory). </p><div class="fragment"><div class="line"><span class="preprocessor">#include &lt;string&gt;</span></div><div class="line"><span class="keyword">using namespace </span><a class="code" href="namespacestd.html">std</a>;</div><div class="line"></div><div class="line"><span class="preprocessor">#include &quot;vlsisapd/agds/Library.h&quot;</span></div><div class="line"><span class="preprocessor">#include &quot;vlsisapd/agds/Structure.h&quot;</span></div><div class="line"><span class="preprocessor">#include &quot;vlsisapd/agds/Rectangle.h&quot;</span></div><div class="line"></div><div class="line"><span class="keywordtype">int</span> main(<span class="keywordtype">int</span> argc, <span class="keywordtype">char</span> * argv[]) {</div><div class="line"> <a class="code" href="class_a_g_d_s_1_1_library.html">AGDS::Library</a>* lib = <span class="keyword">new</span> <a class="code" href="class_a_g_d_s_1_1_library.html">AGDS::Library</a>(<span class="keywordtype">string</span>(<span class="stringliteral">&quot;myTestLib&quot;</span>));</div><div class="line"></div><div class="line"> lib-&gt;<a class="code" href="class_a_g_d_s_1_1_library.html#a0d0e972bb142f892c462bb8d7f04a50b">setUserUnits</a>(0.001);</div><div class="line"> lib-&gt;<a class="code" href="class_a_g_d_s_1_1_library.html#a938acb6eb8d14aade9dba7331c75ff0a">setPhysUnits</a>(1.0E-9);</div><div class="line"></div><div class="line"> <a class="code" href="class_a_g_d_s_1_1_rectangle.html">AGDS::Rectangle</a>* poly = <span class="keyword">new</span> <a class="code" href="class_a_g_d_s_1_1_rectangle.html">AGDS::Rectangle</a>( 17, 305, 150, 365, 830 );</div><div class="line"> <a class="code" href="class_a_g_d_s_1_1_rectangle.html">AGDS::Rectangle</a>* active = <span class="keyword">new</span> <a class="code" href="class_a_g_d_s_1_1_rectangle.html">AGDS::Rectangle</a>( 6, 130, 290, 540, 690 );</div><div class="line"></div><div class="line"> <a class="code" href="class_a_g_d_s_1_1_structure.html">AGDS::Structure</a>* str = <span class="keyword">new</span> <a class="code" href="class_a_g_d_s_1_1_structure.html">AGDS::Structure</a>(<span class="stringliteral">&quot;Transistor&quot;</span>);</div><div class="line"></div><div class="line"> str-&gt;<a class="code" href="class_a_g_d_s_1_1_structure.html#a2dd203e6770f7d15d6f706867c919a60">addElement</a>(poly);</div><div class="line"> str-&gt;<a class="code" href="class_a_g_d_s_1_1_structure.html#a2dd203e6770f7d15d6f706867c919a60">addElement</a>(active);</div><div class="line"></div><div class="line"> lib-&gt;<a class="code" href="class_a_g_d_s_1_1_library.html#a93d333a20154e0b688ff3ff213039171">addStructure</a>(str);</div><div class="line"></div><div class="line"> lib-&gt;<a class="code" href="class_a_g_d_s_1_1_library.html#a33b9d989b84857f46034085664ff3fa2">writeToFile</a>(<span class="stringliteral">&quot;./transistor.agds&quot;</span>);</div><div class="line"> </div><div class="line"> <span class="keywordflow">return</span> 0;</div><div class="line">}</div><div class="line"></div></div><!-- fragment --><dl class="section note"><dt>Note</dt><dd>In order to compile this code, a CMakeLists.txt file is provided. User must set the $VLSISAPD_TOP variable before running these commands in the directory containing the CMakeLists.txt file: <div class="fragment"><div class="line">%&gt; mkdir build; cd build</div><div class="line">%&gt; cmake ..</div><div class="line">%&gt; make</div></div><!-- fragment --></dd></dl>
<h2><a class="anchor" id="agdsPython"></a>
Python</h2>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
2018-10-18 11:10:01 -05:00
<p>Here is the Python code (<code>driveAgds.py</code>) used to generate the transistor.agds file. (Source is available in examples directory). </p><div class="fragment"><div class="line">import AGDS</div><div class="line">lib = <a class="code" href="class_a_g_d_s_1_1_library.html">AGDS.Library</a>(<span class="stringliteral">&quot;myTestLib&quot;</span>)</div><div class="line">lib.setUserUnits(0.001)</div><div class="line">lib.setPhysUnits(1.0e-9)</div><div class="line"></div><div class="line">active = <a class="code" href="class_a_g_d_s_1_1_rectangle.html">AGDS.Rectangle</a>( 6, 120, 290, 540, 690) <span class="comment"># layer 6 corresponds to active</span></div><div class="line">poly = <a class="code" href="class_a_g_d_s_1_1_rectangle.html">AGDS.Rectangle</a>(17, 305, 150, 365, 830) <span class="comment"># layer 17 corresponds to polysilicium</span></div><div class="line"></div><div class="line">str = <a class="code" href="class_a_g_d_s_1_1_structure.html">AGDS.Structure</a>(<span class="stringliteral">&quot;Transistor&quot;</span>)</div><div class="line">str.addElement(active)</div><div class="line">str.addElement(poly)</div><div class="line"></div><div class="line">lib.addStructure(str)</div><div class="line">lib.writeToFile(<span class="stringliteral">&quot;./transistor.agds&quot;</span>)</div></div><!-- fragment --><dl class="section note"><dt>Note</dt><dd>In order to run the <code>driveAgds.py</code> script, user must ensure that $PYTHONPATH variable points to the directory containing AGDS.so module. </dd></dl>
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Migrating the initialisation system to be completely Python-like. * New: In bootstrap/coriolisEnv.py, add the "etc" directory to the PYTHONPATH as initialization are now Python modules. * New: In Hurricane/analogic, first groundwork for the integration of PIP/MIM/MOM multi-capacitors. Add C++ and Python interface for the allocation matrix and the list of capacities values. * Change: In Hurricane::RegularLayer, add a layer parameter to the constructor so the association between the RegularLayer and it's BasicLayer can readily be done. * Change: In Hurricane::Layer, add a new getCut() accessor to get the cut layer in ViaLayer. * Change: In Hurricane::DataBase::get(), the Python wrapper should no longer consider an error if the data-base has not been created yet. Just return None. * Bug: In Isobar::PyLayer::getEnclosure() wrapper, if the overall enclosure is requested, pass the right parameter to the C++ function. * Change: In AllianceFramework, make public _bindLibraries() and export it to the Python interface. * Change: In AllianceFramework::create(), do not longer call bindLibraries(). This now must be done explicitely and afterwards. * Change: In AllianceFramework::createLibrary() and Environement::addSYSTEM_LIBRARY(), minor bug corrections that I don't recall. * Change: In SearchPath::prepend(), set the selected index to zero and return it. * Change: In CRL::System CTOR, add "etc" to the PYTHONPATH as the configuration files are now organized as Python modules. * New: In PyCRL, export the CRL::System singleton, it's creation is no longer triggered by the one of AllianceFramework. * New: In CRL/etc/, convert most of the configuration files into the Python module format. For now, keep the old ".conf", but that are no longer used. For the real technologies, we cannot keep the directory name as "180" or "45" as it not allowed by Python syntax, so we create "node180" or "node45" instead. Most of the helpers and coriolisInit.py are no longer used now. To be removed in future commits after being sure that everything works... * Bug: In AutoSegment::makeDogleg(AutoContact*), the layer of the contacts where badly computed when one end of the original segment was attached to a non-preferred direction segment (mostly on terminal contacts). Now use the new AutoContact::updateLayer() method. * Bug: In Dijkstra::load(), limit symetric search area only if the net is a symmetric one ! * Change: In Katana/python/katanaInit.py, comply with the new initialisation scheme. * Change: In Unicorn/cgt.py, comply to the new inititalization scheme. * Change: In cumulus various Python scripts remove the call to helpers.staticInitialization() as they are not needed now (we run in only *one* interpreter, so we correctly share all init). In plugins/__init__.py, read the new NDA directory variable. * Bug: In cumulus/plugins/Chip.doCoronafloorplan(), self.railsNb was not correctly managed when there was no clock. * Change: In cumulus/plugins/Configuration.coronaContactArray(), compute the viaPitch from the technology instead of the hard-coded 4.0 lambdas. In Configuration.loadConfiguration(), read the "ioring.py" from the new user's settings module. * Bug: In stratus.dpgen_ADSB2F, gives coordinates translated into DbU to the XY functions. In st_model.Save(), use the VstUseConcat flag to get correct VST files. In st_net.hur_net(), when a net is POWER/GROUND or CLOCK also make it global. * Change: In Oroshi/python/WIP_Transistor.py, encapsulate the generator inside a try/except block to get prettier error (and stop at the first).
2019-10-28 12:09:14 -05:00
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