2012-11-16 06:49:47 -06:00
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Added support for multiple symbolic+real technology in configuration.
In CRL Core, the layout of the files under "/coriolis2/etc" changes.
Instead of having them directly under "etc", they are now replicated,
in subdirectories. Each subdirectory having the name of the associated
symbolic or real technology (they are kept separated). We have, for
now:
* etc/cmos/ : symbolic, the Alliance original one.
* etc/vsc200/ : symbolic, for G. Petley vsclib.
* etc/hcmos9/ : real, generic fake (130nm).
To tell which pair (symbolic,real) technologies must be used we create
a *second* (sigh) configuration file "coriolis2_techno.conf", and it's
hidden counterpart in the user's account, to set it up. It needs to be
separate because it is read as early as possible and select which set
of configuration files would be read.
Also add support up to METAL8 and POLY2 in CRL core and it's Alliance
parser/drivers.
2014-05-21 07:50:22 -05:00
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install ( FILES coriolis2_techno.conf DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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2014-05-21 17:13:17 -05:00
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install ( DIRECTORY common DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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Added support for multiple symbolic+real technology in configuration.
In CRL Core, the layout of the files under "/coriolis2/etc" changes.
Instead of having them directly under "etc", they are now replicated,
in subdirectories. Each subdirectory having the name of the associated
symbolic or real technology (they are kept separated). We have, for
now:
* etc/cmos/ : symbolic, the Alliance original one.
* etc/vsc200/ : symbolic, for G. Petley vsclib.
* etc/hcmos9/ : real, generic fake (130nm).
To tell which pair (symbolic,real) technologies must be used we create
a *second* (sigh) configuration file "coriolis2_techno.conf", and it's
hidden counterpart in the user's account, to set it up. It needs to be
separate because it is read as early as possible and select which set
of configuration files would be read.
Also add support up to METAL8 and POLY2 in CRL core and it's Alliance
parser/drivers.
2014-05-21 07:50:22 -05:00
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install ( DIRECTORY cmos DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( DIRECTORY vsc200 DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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2014-08-03 09:36:21 -05:00
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install ( DIRECTORY scmos_deep_018 DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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Correction in plugins to support msxlib compatible pads.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
variable to define the pad model name extension ("px" for "sxlib
and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
of used for power & clock supply. We may remove the extention in
the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
longer place the accessing contact *at the center* of the
RoutingPad. It works under sxlib because buffers & registers all
have same size terminals. But this is not true under vsxlib,
leading to misaligned contacts & wires. Now systematically place
on the slice midlle track (maybe with one pitch above or below).
This is still very weak as we do not check if the terminal
reach were the contact is being put. Has to be strenthened in
the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
of PyInt for DbU conversions. In PyHurricane argument converter,
automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
in case of discrepency in global net connections (i.e. no net
of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
model name to find "pck_" or "pvddeck_", do not compare the
extension part. But we still use hard-coded stem pad names,
maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
RoutingPads of fixed nets, they are already through the
BuildPowerRails stage (and it's causing scary overlap warning
messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
deep-plug when the core is flat (not sub-modules). All the new
nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
that the core is aligned on the GCell grid (i.e. the slice
grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
while looking for the bigger N-E RoutingPad. Forgot to decrement
the index...
2014-09-13 10:45:30 -05:00
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install ( DIRECTORY scn6m_deep_09 DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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Added support for multiple symbolic+real technology in configuration.
In CRL Core, the layout of the files under "/coriolis2/etc" changes.
Instead of having them directly under "etc", they are now replicated,
in subdirectories. Each subdirectory having the name of the associated
symbolic or real technology (they are kept separated). We have, for
now:
* etc/cmos/ : symbolic, the Alliance original one.
* etc/vsc200/ : symbolic, for G. Petley vsclib.
* etc/hcmos9/ : real, generic fake (130nm).
To tell which pair (symbolic,real) technologies must be used we create
a *second* (sigh) configuration file "coriolis2_techno.conf", and it's
hidden counterpart in the user's account, to set it up. It needs to be
separate because it is read as early as possible and select which set
of configuration files would be read.
Also add support up to METAL8 and POLY2 in CRL core and it's Alliance
parser/drivers.
2014-05-21 07:50:22 -05:00
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install ( DIRECTORY hcmos9 DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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2012-11-16 06:49:47 -06:00
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Added support for multiple symbolic+real technology in configuration.
In CRL Core, the layout of the files under "/coriolis2/etc" changes.
Instead of having them directly under "etc", they are now replicated,
in subdirectories. Each subdirectory having the name of the associated
symbolic or real technology (they are kept separated). We have, for
now:
* etc/cmos/ : symbolic, the Alliance original one.
* etc/vsc200/ : symbolic, for G. Petley vsclib.
* etc/hcmos9/ : real, generic fake (130nm).
To tell which pair (symbolic,real) technologies must be used we create
a *second* (sigh) configuration file "coriolis2_techno.conf", and it's
hidden counterpart in the user's account, to set it up. It needs to be
separate because it is read as early as possible and select which set
of configuration files would be read.
Also add support up to METAL8 and POLY2 in CRL core and it's Alliance
parser/drivers.
2014-05-21 07:50:22 -05:00
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install ( FILES environment.alliance.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( FILES technology.symbolic.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( FILES technology.cmos130.s2r.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( FILES technology.cmos65.s2r.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( FILES technology.ams035.s2r.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( FILES technology.freePDK45.s2r.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( FILES technology.fake.s2r.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( FILES display.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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install ( FILES tools.configuration.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 )
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