59 lines
2.2 KiB
TeX
59 lines
2.2 KiB
TeX
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\begin{itemize}
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\item Name : DpgenAdsb2f -- Adder/Substractor Macro-Generator
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\item Description : Generates a \verb-n- bits adder/substractor named \verb-modelname-.
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\item How it works :
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\begin{itemize}
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\item if the \verb-add_sub- signal is set to \verb-zero- an addition is performed, otherwise it's a substraction.
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\item Operation can be either signed or unsigned. In unsigned mode \verb-c31- is the overflow. in signed mode you have to compute overflow by \emph{XORing} \verb-c31- and \verb-c30-
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\end{itemize}
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\item Terminal Names :
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\begin{itemize}
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\item add\_sub : select addition or substraction (input, 1 bit)
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\item c31 : carry out. In unsigned mode, this is the overflow (output, 1 bit)
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\item c30 : used to compute overflow in signed mode : \verb-overflow = c31 xor c30- (output, 1 bit)
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\item i0 : first operand (input, \verb-n- bits)
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\item i1 : second operand (input, \verb-n- bits)
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\item q : output (\verb-n- bits)
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\item vdd : power
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\item vss : ground
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\end{itemize}
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\item Parameters : Parameters are given with a map called \verb-param-.
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\begin{itemize}
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\item nbit : Defines the size of the generator
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\end{itemize}
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% \item Behavior :
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%\begin{verbatim}
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%\end{verbatim}
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\item Example :
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\begin{verbatim}
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class myClass ( Model ) :
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def Interface ( self ) :
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self._in = LogicIn ( "in", 8 )
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self._in2 = LogicIn ( "in2", 8 )
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self._out = LogicOut ( "out", 8 )
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self._as = LogicIn ( "as", 1 )
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self._c0 = LogicOut ( "c0", 1 )
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self._c1 = LogicOut ( "c1", 1 )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Inst ( 'DpgenAdsb2f'
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, param = { 'nbit' : 8 }
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, map = { 'i0' : self._in
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, 'i1' : self._in2
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, 'add_sub' : self._as
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, 'q' : self._out
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, 'c30' : self._c0
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, 'c31' : self._c1
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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\end{verbatim}
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\end{itemize}
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