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< title > Coriolis < span class = "sc" > vlsi< / span > Backend Tools - Coriolis VLSI CAD Tools [offline]< / title >
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< li > < a class = "reference internal" href = "#abstract" id = "id2" > Abstract< / a > < ul >
< li > < a class = "reference internal" href = "#design-flow" id = "id3" > Design Flow< / a > < / li >
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< li > < a class = "reference internal" href = "#design-features-of-coriolis" id = "id4" > Design & Features of < span class = "sc" > Coriolis< / span > < / a > < / li >
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< p > < span class = "sc" > Alliance< / span > is a complete toolchain for < span class = "sc" > vlsi< / span > design. It provides a < span class = "sc" > vhdl< / span > compiler
and simulator, logic synthetiser, automatic place & route and portable < span class = "sc" > cmos< / span >
library. It has been in used in research projects such as the 875K transistors
< span class = "sc" > StaCS< / span > superscalar microprocessor or the 400K transistors < span class = "sc" > ieee< / span > gigabit < span class = "sc" > hsl< / span >
router. It has been actively developped during the 1990-2000 years and is maintained
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since. Its practical limit for one standard cell block (flat) is about 10K gates,
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above that limit you would need to use hierarchy and manually build a floorplan.
< span class = "sc" > Alliance< / span > is entirely written in C.< / p >
< p > < span class = "sc" > Coriolis< / span > was started in the year 2000 as a replacement for the place & route stage
of < span class = "sc" > Alliance< / span > . As such it is able to handle standard cells block (flat) of at least 150K
gates. It was later extended to support analog design re-implementing the methodology
introduced by the < span class = "sc" > cian< / span > team of < span class = "sc" > lip6< / span > / < span class = "sc" > su< / span > in < span class = "sc" > cairo< / span > / < span class = "sc" > cairo+< / span > . The tools have
been designed from the ground up to support digital only, analog only or mixed circuits.
< span class = "sc" > Coriolis< / span > is written in a mix of C++ and < span class = "sc" > Python< / span > .< / p >
< p > < span class = "sc" > Alliance< / span > / < span class = "sc" > Coriolis< / span > is free software. All source code is realeased under the < a class = "reference external" href = "http://www.gnu.org/copyleft/gpl.txt" > GPL< / a >
license, except for < span class = "sc" > Hurricane< / span > which is under < a class = "reference external" href = "https://www.gnu.org/licenses/lgpl-3.0.html" > LGPL< / a > and the < a class = "reference external" href = "http://www.si2.org/" > Si2< / a > < span class = "sc" > lef< / span > / < span class = "sc" > def< / span >
parser drivers that are under < a class = "reference external" href = "http://www.apache.org/licences/LICENSE-2.0" > Apache License, Version 2.0< / a > .< / p >
< p > < a class = "reference external" href = "../pages/symbolic-layout.html" > Short introduction to Symbolic Layout.< / a > < / p >
< div class = "section" id = "design-flow" >
< h3 > < a class = "toc-backref" href = "#id3" > Design Flow< / a > < / h3 >
< p > We are also upgrading the complete design flow by replacing < span class = "sc" > Alliance< / span > obsoleting
tools by more advanced < span class = "sc" > foss< / span > alternatives:< / p >
< ul class = "simple" >
< li > < a class = "reference external" href = "http://www.clifford.at/yosys/" > Yosys< / a > for logical synthesis.< / li >
< li > < a class = "reference external" href = "https://github.com/ghdl/ghdl" > GHDL< / a > for < span class = "sc" > vhdl< / span > simulation.< / li >
< / ul >
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< h2 > < a class = "toc-backref" href = "#id4" > Design & Features of < span class = "sc" > Coriolis< / span > < / a > < / h2 >
< p > The < span class = "sc" > Coriolis< / span > toolchain is build upon the < span class = "sc" > Hurricane< / span > database.< / p >
< ul class = "simple" >
< li > < strong > Tool Integration.< / strong > To better manages the challenges arising in the
increasingly bigger designs, the various tools have to work together
as a whole, in a tight integration at runtime. The < span class = "sc" > Hurricane< / span > database
has been develop to address this problem and as a results, all < span class = "sc" > Coriolis< / span >
tools are built upon it and can communicate through that core database.< / li >
< li > < strong > Deterministic.< / strong > The database and the tools are completely deterministics.
Two runs in < em > exactly< / em > the same context gives the same result.< / li >
< li > < strong > C++ & Python.< / strong > The < span class = "sc" > Hurricane< / span > database and all tools are fully exported
in < span class = "sc" > Python< / span > providing a seamless integration. The whole toolchain is build
as a mix of C++ for computational intensive part and < span class = "sc" > Python< / span > scripts for
everything else. There is not even a binary, the main program < em > is< / em > a
< span class = "sc" > Python< / span > script and can be rewritten in any way you like.< / li >
< li > < strong > Graphic Interface.< / strong > < span class = "sc" > Hurricane< / span > also come with a graphical interface
allowing to display, explore or check your design. The graphic interface
can be extended (in C++) do display any custom overlay.< / li >
< li > < strong > Symbolic Layout.< / strong > For digital part of the designs, we use a symbolic
layer approach. Note that < span class = "sc" > Coriolis< / span > can make digital designs using real
technology, but it's a largely untested feature yet.< / li >
< li > < strong > Analog Design.< / strong > A complete user-guided methodology for designing analog
circuits is available. It is fully integrated in all the tools and will
allow mixed design in the near future.< / li >
< / ul >
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< h2 > < a class = "toc-backref" href = "#id5" > Disclaimer< / a > < / h2 >
< p > < span class = "sc" > Alliance< / span > / < span class = "sc" > Coriolis< / span > tools, at the time being, are not suitable for deep submicron
technological nodes (below 130nm / 180nm).< / p >
< p > For portability across foundries, technological nodes and freedom from fondries < span class = "sc" > nda< / span > ,
< span class = "sc" > Alliance< / span > / < span class = "sc" > Coriolis< / span > rely on < em > portable< / em > layout (or < em > scalable< / em > layout, or < em > symbolic< / em > layout).
To produce a valid < span class = "sc" > gds< / span > file, you would need to use the < span class = "cb" > s2r< / span > translation tool which
needs a configuration file suited for the target technology, and < em > that< / em > file is under
< span class = "sc" > nda< / span > . So, either should be written by you, or given to you through services like
< a class = "reference external" href = "https://www.mycmp.fr/" > MyCMP< / a > .< / p >
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