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Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
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<!DOCTYPE HTML PUBLIC '-//W3C//DTD HTML 4.0//EN'>
<html>
<head>
<meta http-equiv="Content-Type" content="text/html;charset=utf-8">
<title>VLSI SAPD Documentation</title>
<link href="stylesheet.css" rel="stylesheet" type="text/css">
</head>
<h1 id="pagetop" class="header">VLSI SAPD Documentation</h1>
<center class="header">
<table class="header">
<tr>
<td><a href="index.html">Presentation</a></td>
<td><a href="agds.html">AGDS</a></td>
<td><a href="cif.html">CIF</a></td>
<td><a href="dtr.html">DTR</a></td>
<td><a href="openchams.html">OPENCHAMS</a></td>
<td><a href="spice.html">SPICE</a></td>
<td><a href="contact.html">Links & Contact</a></td>
</tr>
</table>
</center>
<br>
<hr>
<body>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<!-- Generated by Doxygen 1.8.14 -->
Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
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</div><!-- top -->
<div class="header">
<div class="headertitle">
<div class="title">CIF Format </div> </div>
</div><!--header-->
<div class="contents">
<div class="textblock"><h1><a class="anchor" id="cifPres"></a>
Presentation</h1>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>The <b>Caltech Intermediate Format (CIF)</b> consists in a limited set of graphic primitives used to describe the shapes on each layer of an integrated circuit (see <a href="http://en.wikipedia.org/wiki/Caltech_Intermediate_Form">http://en.wikipedia.org/wiki/Caltech_Intermediate_Form</a> for more informations). <br />
Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
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</p>
<h2><a class="anchor" id="cifAutrhos"></a>
Author</h2>
<p>Damien Dupuis: damien.dupuis(at)lip6(.)fr</p>
<h2><a class="anchor" id="cifLimits"></a>
Limitations</h2>
<p>Although the CIF format allows hierarchical description and supports several shapes, in this driver, we do not use hierarchy and only use Polygons.</p>
<h1><a class="anchor" id="cifDB"></a>
Stand alone database structure</h1>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>The database consists in two simple objects :</p><ul>
Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
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<li><a class="el" href="class_c_i_f_1_1_circuit.html">CIF::Circuit</a> contains all CIF circuit informations such as the name, the unit used, the scale and the list of all Polygons.</li>
<li><a class="el" href="class_c_i_f_1_1_polygon.html">CIF::Polygon</a> describes a Polygon (a set of points).</li>
</ul>
<h2><a class="anchor" id="cifDriver"></a>
Using the driver</h2>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>To drive a CIF file, user has to create one <a class="el" href="class_c_i_f_1_1_circuit.html">CIF::Circuit</a> and as many <a class="el" href="class_c_i_f_1_1_polygon.html">CIF::Polygon</a> as the number of shapes of the layout. The <a class="el" href="class_c_i_f_1_1_polygon.html">CIF::Polygon</a> objects can be created independently from for the <a class="el" href="class_c_i_f_1_1_circuit.html">CIF::Circuit</a> but must be finally added to the <a class="el" href="class_c_i_f_1_1_circuit.html">CIF::Circuit</a> using <a class="el" href="class_c_i_f_1_1_circuit.html#a5b37e86206e2a128ba6db4987dc09a39" title="adds a Polygon to the Circuit. ">CIF::Circuit::addPolygon()</a>.<br />
Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
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Once the <a class="el" href="class_c_i_f_1_1_circuit.html">CIF::Circuit</a> is complete, simply call the <a class="el" href="class_c_i_f_1_1_circuit.html#a90c823b70c4984f302c19ceca604d101" title="writes the database to file. ">CIF::Circuit::writeToFile()</a> method to drive the database to file.</p>
<h1><a class="anchor" id="cifExamples"></a>
Examples</h1>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>As said is the global presentation, VLSI SAPD project provides C++ libraries and Python modules for each supported format. In this section we present two simple code examples to drive a CIF file using C++ or Python. These two examples drive the same file <code>transistor.cif:</code> </p><div class="fragment"><div class="line">(CIF file written on 11-Jun-2010 13:49:44 by VLSISAPD_CIF_DRIVER);</div><div class="line">(Units: micro - UU/DB Scale: 0.001);</div><div class="line">DS 1 1 1;</div><div class="line">9 Transistor;</div><div class="line">L 6; P 130,290 540,290 540,690 130,690;</div><div class="line">L 17; P 305,150 365,150 365,830 305,830;</div><div class="line">DF;</div><div class="line">C 1;</div><div class="line">E</div></div><!-- fragment --><div class="image">
Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
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<img src="transistorCif.png" alt="transistorCif.png"/>
<div class="caption">
CIF example layout</div></div>
<h2><a class="anchor" id="cifC"></a>
C++</h2>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
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<p>Here is the C++ code (<code>driveCif.cpp</code>) used to generate the transistor.cif file. (Source is available in examples directory). </p><div class="fragment"><div class="line"><span class="preprocessor">#include &lt;string&gt;</span></div><div class="line"><span class="keyword">using namespace </span><a class="code" href="namespacestd.html">std</a>;</div><div class="line"></div><div class="line"><span class="preprocessor">#include &quot;vlsisapd/cif/Circuit.h&quot;</span></div><div class="line"><span class="preprocessor">#include &quot;vlsisapd/cif/Polygon.h&quot;</span></div><div class="line"></div><div class="line"><span class="keywordtype">int</span> main(<span class="keywordtype">int</span> argc, <span class="keywordtype">char</span> * argv[]) {</div><div class="line"> <a class="code" href="class_c_i_f_1_1_circuit.html">CIF::Circuit</a>* circuit = <span class="keyword">new</span> <a class="code" href="class_c_i_f_1_1_circuit.html">CIF::Circuit</a>(<span class="keywordtype">string</span>(<span class="stringliteral">&quot;Transistor&quot;</span>), <span class="keywordtype">string</span>(<span class="stringliteral">&quot;micro&quot;</span>), 0.001);</div><div class="line"></div><div class="line"> <span class="comment">// Layer #6 corresponds to active</span></div><div class="line"> <a class="code" href="class_c_i_f_1_1_polygon.html">CIF::Polygon</a>* poly = <span class="keyword">new</span> <a class="code" href="class_c_i_f_1_1_polygon.html">CIF::Polygon</a>(6);</div><div class="line"> poly-&gt;<a class="code" href="class_c_i_f_1_1_polygon.html#ab3047469780327f18539907e1303ea15">addPoint</a>(130, 290);</div><div class="line"> poly-&gt;<a class="code" href="class_c_i_f_1_1_polygon.html#ab3047469780327f18539907e1303ea15">addPoint</a>(540, 290);</div><div class="line"> poly-&gt;<a class="code" href="class_c_i_f_1_1_polygon.html#ab3047469780327f18539907e1303ea15">addPoint</a>(540, 690);</div><div class="line"> poly-&gt;<a class="code" href="class_c_i_f_1_1_polygon.html#ab3047469780327f18539907e1303ea15">addPoint</a>(130, 690);</div><div class="line"> circuit-&gt;<a class="code" href="class_c_i_f_1_1_circuit.html#a5b37e86206e2a128ba6db4987dc09a39">addPolygon</a>(poly);</div><div class="line"></div><div class="line"> <span class="comment">// Layer #17 corresponds to polysilicium</span></div><div class="line"> poly = <span class="keyword">new</span> <a class="code" href="class_c_i_f_1_1_polygon.html">CIF::Polygon</a>(17);</div><div class="line"> poly-&gt;<a class="code" href="class_c_i_f_1_1_polygon.html#ab3047469780327f18539907e1303ea15">addPoint</a>(305, 150);</div><div class="line"> poly-&gt;<a class="code" href="class_c_i_f_1_1_polygon.html#ab3047469780327f18539907e1303ea15">addPoint</a>(365, 150);</div><div class="line"> poly-&gt;<a class="code" href="class_c_i_f_1_1_polygon.html#ab3047469780327f18539907e1303ea15">addPoint</a>(365, 830);</div><div class="line"> poly-&gt;<a class="code" href="class_c_i_f_1_1_polygon.html#ab3047469780327f18539907e1303ea15">addPoint</a>(305, 830);</div><div class="line"> circuit-&gt;<a class="code" href="class_c_i_f_1_1_circuit.html#a5b37e86206e2a128ba6db4987dc09a39">addPolygon</a>(poly);</div><div class="line"></div><div class="line"> circuit-&gt;<a class="code" href="class_c_i_f_1_1_circuit.html#a90c823b70c4984f302c19ceca604d101">writeToFile</a>(<span class="stringliteral">&quot;./transistor.cif&quot;</span>);</div><div class="line"> </div><div class="line"> <span class="keywordflow">return</span> 0;</div><div class="line">}</div><div class="line"></div></div><!-- fragment --><dl class="section note"><dt>Note</dt><dd>In order to compile this code, a CMakeLists.txt file is provided. User must set the $VLSISAPD_TOP variable before running these commands in the directory containing the CMakeLists.txt file: <div class="fragment"><div class="line">%&gt; mkdir build; cd build</div><div class="line">%&gt; cmake ..</div><div class="line">%&gt; make</div></div><!-- fragment --></dd></dl>
Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
2018-06-06 11:42:26 -05:00
<h2><a class="anchor" id="cifPython"></a>
Python</h2>
Analog integration part II. Analog place & route (slicing tree). * Change: In Hurricane::CellWidget, set the minimal size to 350 pixels to fit my normal DPI secondary screen... * Change: In Hurricane::Error(), reactivate the backtrace generation by default. Seriously slow down the program each time an Error is to be constructed. * Bug: In Analog::Device::preCreate(), check for NULL Technology before attempting to use it. * Change: In Hurricane/Analog, remove all '*Arguments*' classes and their Python interface. It was an obsoleted way of passing devices parameters to the Python layout generators (located in Oroshi). Now we just get them straight from the Device with the getParamter() method. * Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze. * Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove all uses of the "Arguments". Directly access the parameters through the device itself. Make the checkCoherency() with identical arguments as of layout(). * New: Bora tool that performs analog place & route. Based on a slicing tree representation. It is the thesis work of Eric Lao. Code beautyfication and some programming cleanup. * New: Karakaze tool, provide the Python base class AnalogDesign used to build an analog design. Create/configure devices and assemble them in a slicing tree. * Change: In Unicorn/cgt.py, display the stack trace in case of an ImportError exception as well as for other exceptions. Add Bora to the set for included tool engines.
2018-10-18 11:10:01 -05:00
<p>Here is the Python code (<code>driveCif.py</code>) used to generate the transistor.cif file. (Source is available in examples directory). </p><div class="fragment"><div class="line"><span class="keyword">import</span> CIF</div><div class="line">circuit = <a class="code" href="class_c_i_f_1_1_circuit.html">CIF.Circuit</a>(<span class="stringliteral">&quot;Transistor&quot;</span>, <span class="stringliteral">&quot;micro&quot;</span>, 0.001)</div><div class="line">poly1 = <a class="code" href="class_c_i_f_1_1_polygon.html">CIF.Polygon</a>(6)</div><div class="line">poly1.addPoint(130, 290)</div><div class="line">poly1.addPoint(540, 290)</div><div class="line">poly1.addPoint(540, 690)</div><div class="line">poly1.addPoint(130, 690)</div><div class="line">circuit.addPolygon(poly1)</div><div class="line"> </div><div class="line">poly2 = <a class="code" href="class_c_i_f_1_1_polygon.html">CIF.Polygon</a>(17)</div><div class="line">poly2.addPoint(305, 150);</div><div class="line">poly2.addPoint(365, 150);</div><div class="line">poly2.addPoint(365, 830);</div><div class="line">poly2.addPoint(305, 830);</div><div class="line">circuit.addPolygon(poly2)</div><div class="line"></div><div class="line">circuit.writeToFile(<span class="stringliteral">&quot;./transistor.cif&quot;</span>)</div></div><!-- fragment --><dl class="section note"><dt>Note</dt><dd>In order to run the <code>driveCif.py</code> script, user must ensure that $PYTHONPATH variable points to the directory containing CIF.so module. </dd></dl>
Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
2018-06-06 11:42:26 -05:00
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Migrating the initialisation system to be completely Python-like. * New: In bootstrap/coriolisEnv.py, add the "etc" directory to the PYTHONPATH as initialization are now Python modules. * New: In Hurricane/analogic, first groundwork for the integration of PIP/MIM/MOM multi-capacitors. Add C++ and Python interface for the allocation matrix and the list of capacities values. * Change: In Hurricane::RegularLayer, add a layer parameter to the constructor so the association between the RegularLayer and it's BasicLayer can readily be done. * Change: In Hurricane::Layer, add a new getCut() accessor to get the cut layer in ViaLayer. * Change: In Hurricane::DataBase::get(), the Python wrapper should no longer consider an error if the data-base has not been created yet. Just return None. * Bug: In Isobar::PyLayer::getEnclosure() wrapper, if the overall enclosure is requested, pass the right parameter to the C++ function. * Change: In AllianceFramework, make public _bindLibraries() and export it to the Python interface. * Change: In AllianceFramework::create(), do not longer call bindLibraries(). This now must be done explicitely and afterwards. * Change: In AllianceFramework::createLibrary() and Environement::addSYSTEM_LIBRARY(), minor bug corrections that I don't recall. * Change: In SearchPath::prepend(), set the selected index to zero and return it. * Change: In CRL::System CTOR, add "etc" to the PYTHONPATH as the configuration files are now organized as Python modules. * New: In PyCRL, export the CRL::System singleton, it's creation is no longer triggered by the one of AllianceFramework. * New: In CRL/etc/, convert most of the configuration files into the Python module format. For now, keep the old ".conf", but that are no longer used. For the real technologies, we cannot keep the directory name as "180" or "45" as it not allowed by Python syntax, so we create "node180" or "node45" instead. Most of the helpers and coriolisInit.py are no longer used now. To be removed in future commits after being sure that everything works... * Bug: In AutoSegment::makeDogleg(AutoContact*), the layer of the contacts where badly computed when one end of the original segment was attached to a non-preferred direction segment (mostly on terminal contacts). Now use the new AutoContact::updateLayer() method. * Bug: In Dijkstra::load(), limit symetric search area only if the net is a symmetric one ! * Change: In Katana/python/katanaInit.py, comply with the new initialisation scheme. * Change: In Unicorn/cgt.py, comply to the new inititalization scheme. * Change: In cumulus various Python scripts remove the call to helpers.staticInitialization() as they are not needed now (we run in only *one* interpreter, so we correctly share all init). In plugins/__init__.py, read the new NDA directory variable. * Bug: In cumulus/plugins/Chip.doCoronafloorplan(), self.railsNb was not correctly managed when there was no clock. * Change: In cumulus/plugins/Configuration.coronaContactArray(), compute the viaPitch from the technology instead of the hard-coded 4.0 lambdas. In Configuration.loadConfiguration(), read the "ioring.py" from the new user's settings module. * Bug: In stratus.dpgen_ADSB2F, gives coordinates translated into DbU to the XY functions. In st_model.Save(), use the VstUseConcat flag to get correct VST files. In st_net.hur_net(), when a net is POWER/GROUND or CLOCK also make it global. * Change: In Oroshi/python/WIP_Transistor.py, encapsulate the generator inside a try/except block to get prettier error (and stop at the first).
2019-10-28 12:09:14 -05:00
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Add a fully generated documentation in the git repository. * Change: In all tools supplying documentation, as we use some specific software to create the doc, they may not be available, or worse, be and incompatible version. So, by default, we install the files shipped with the git repository. To force a full doc rebuild, use the "--doc" flag of ccb.py.
2018-06-06 11:42:26 -05:00
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