# DpgenBuff

- Name : DpgenBuff - Buffer Macro-Generator
- Synopsys :

      Generate ( 'DpgenBuff', modelname
               , param = { 'nbit'       : n
                         , 'drive'      : d
                         , 'physical'   : True
                         , 'behavioral' : True
                         }
               )

- Description : Generates a `n` bits inverter with an output power of `d` named `modelname`.
- Terminal Names :
  - i0 : input (`n` bits)
  - q : output (`n` bits)
  - vdd : power
  - vss : ground
- Parameters : Parameters are given in the map `param`.
  - nbit (mandatory) : Defines the size of the generator
  - drive (optional) : Defines the output power of the gates
    - Valid drive are : 2, 4 or 8
    - If this parameter is not defined, it's value is the smallest one permitted
  - physical (optional, default value : False) : In order to generate a layout
  - behavioral (optional, default value : False) : In order to generate a behavior
- Behavior :

      nq <= i0

- Example :

      from stratus import *

      class inst_buff ( Model ) :

        def Interface ( self ) :
          self.i = SignalIn  ( "i", 32 )
          self.o = SignalOut ( "o", 32 )

          self.vdd = VddIn ( "vdd" )
          self.vss = VssIn ( "vss" )

        def Netlist ( self ) :
          Generate ( 'DpgenBuff', 'buff_32'
                   , param = { 'nbit'     : 32
                             , 'physical' : True
                             }
                   )
          self.I = Inst ( 'buff_32', 'inst'
                        , map = { 'i0'  : self.i
                                , 'q'   : self.o
                                , 'vdd' : self.vdd
                                , 'vss' : self.vss
                                }
                        )

        def Layout ( self ) :
          Place ( self.I, NOSYM, Ref(0, 0) )