# DpgenRf1d

- Name : DpgenRf1d, DpgenRf1dr0 - Register File with Decoder Macro-Generator
- Synopsys :

      Generate ( 'DpgenRf1d', modelname
               , param = { 'nbit'     : n
                         , 'nword'    : regNumber
                         , 'physical' : True
                         }
               )

- Description : Generates a register file of `regNumber` words of `n` bits with decoder named `modelname`.
- Terminal Names :
  - ck : clock signal (input, 1 bit)
  - sel : select the write bus (input, 1 bit)
  - wen : write enable (input, 1 bit)
  - ren : read enable (input, 1 bit)
  - adr : the read address (input, `Y` bits)
  - adw : the write address (input, `Y` bits)
  - datain0 : first write bus (input, `n` bits)
  - datain1 : second write bus (input, `n` bits)
  - dataout : read bus (output, `n` bits)
  - vdd : power
  - vss : ground
- Parameters : Parameters are given in the map `param`.
  - nbit (mandatory) : Defines the size of the words (even, between 2 and 64)
  - nword (mandatory) : Defines the number of the words (even, between 6 and 32)
  - physical (optional, default value : False) : In order to generate a layout
- How it works :
  - datain0 and datain1 are the two write busses. Only one is used to actually write the register word, it is selected by the sel signal.
  - When sel is set to zero datain0 is used to write the register word, otherwise it will be datain1
  - adr, adw : the width (Y) of those signals is computed from regNumber : `Y = log2(regNumber)`
  - wen and ren : write enable and read enable, allows reading and writing when sets to `one`
  - The DpgenRf1dr0 variant differs from the DpgenRf1d in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero
- Example :

      from stratus import *

      class inst_rf1d ( Model ) :

        def Interface ( self ) :
          self.ck      = SignalIn  (       "ck", 1 )
          self.sel     = SignalIn  (      "sel", 1 )
          self.wen     = SignalIn  (      "wen", 1 )
          self.ren     = SignalIn  (      "ren", 1 )
          self.adr     = SignalIn  (      "adr", 4 )
          self.adw     = SignalIn  (      "adw", 4 )
          self.datain0 = SignalIn  (  "datain0", 4 )
          self.datain1 = SignalIn  (  "datain1", 4 )
          self.dataout = SignalOut (  "dataout", 4 )

          self.vdd = VddIn ( "vdd" )
          self.vss = VssIn ( "vss" )

        def Netlist ( self ) :
          Generate ( 'DpgenRf1d', 'rf1d_4_16'
                   , param = { 'nbit'     : 4
                             , 'nword'    : 16
                             , 'physical' : True
                             }
                   )
          self.I = Inst ( 'rf1d_4_16', 'inst'
                        , map = { 'ck'      : self.ck
                                , 'sel'     : self.sel
                                , 'wen'     : self.wen
                                , 'ren'     : self.ren
                                , 'adr'     : self.adr
                                , 'adw'     : self.adw
                                , 'datain0' : self.datain0
                                , 'datain1' : self.datain1
                                , 'dataout' : self.dataout
                                , 'vdd'     : self.vdd
                                , 'vss'     : self.vss
                                }
                        )

        def Layout ( self ) :
          Place ( self.I, NOSYM, Ref(0, 0) )