# DpgenBuse

- Name : DpgenBuse - Tristate Macro-Generator
- Synopsys :

      Generate ( 'DpgenBuse', modelname
               , param = { 'nbit'       : n
                         , 'physical'   : True
                         , 'behavioral' : True
                         }
               )

- Description : Generates a `n` bits tristate named `modelname`.
- Terminal Names :
  - cmd : select ( 1 bit )
  - i0 : input ( `n` bits )
  - q : output ( `n` bits )
  - vdd : power
  - vss : ground
- Parameters : Parameters are given in the map `param`.
  - nbit (mandatory) : Defines the size of the generator
  - physical (optional, default value : False) : In order to generate a layout
  - behavioral (optional, default value : False) : In order to generate a behavior
- Behavior :

      nts:BLOCK(cmd = '1') BEGIN
          q <= GUARDED i0;
      END

- Example :

      from stratus import *

      class inst_buse ( Model ) :

        def Interface ( self ) :
          self.i   = SignalIn  (   "i", 8 )
          self.cmd = SignalIn  ( "cmd", 1 )
          self.o   = SignalOut (   "o", 8 )

          self.vdd = VddIn ( "vdd" )
          self.vss = VssIn ( "vss" )

        def Netlist ( self ) :
          Generate ( 'DpgenBuse', 'buse_8'
                   , param = { 'nbit'     : 8
                             , 'physical' : True
                             }
                   )
          self.I = Inst ( 'buse_8', 'inst'
                        , map = { 'i0'  : self.i
                                , 'cmd' : self.cmd
                                , 'q'   : self.o
                                , 'vdd' : self.vdd
                                , 'vss' : self.vss
                                }
                        )

        def Layout ( self ) :
          Place ( self.I, NOSYM, Ref(0, 0) )