# DpgenAdsb2f

- Name : DpgenAdsb2f - Adder/Substractor Macro-Generator
- Synopsys :

      Generate ( 'DpgenAdsb2f', modelname
               , param = { 'nbit'       : n
                         , 'physical'   : True
                         , 'behavioral' : True
                         }
               )

- Description : Generates a `n` bits adder/substractor named `modelname`.
- Terminal Names :
  - i0 : First operand (input, `n` bits)
  - i1 : Second operand (input, `n` bits)
  - q : Output operand (ouput, `n` bits)
  - add_sub : Select addition or substraction (input, 1 bit)
  - c31 : Sarry out. In unsigned mode, this is the overflow (output, 1 bit)
  - c30 : Used to compute overflow in signed mode : `overflow = c31 xor c30` (output, 1 bit)
  - vdd : power
  - vss : ground
- Parameters : Parameters are given in the map `param`.
  - nbit (mandatory) : Defines the size of the generator
  - physical (optional, default value : False) : In order to generate a layout
  - behavioral (optional, default value : False) : In order to generate a behavior
- How it works :
  - If the `add_sub` signal is set to `zero`, an addition is performed, otherwise it's a substraction.
  - Operation can be either signed or unsigned. In unsigned mode `c31` is the overflow ; in signed mode you have to compute overflow by XORing `c31` and `c30`
- Example :

      from stratus import *

      class inst_ADSB2F ( Model ) :

        def Interface ( self ) :
          self.in1 = SignalIn  ( "in1", 8 )
          self.in2 = SignalIn  ( "in2", 8 )
          self.out = SignalOut (   "o", 8 )
          self.as  = SignalIn  (  "as", 1 )
          self.c0  = SignalOut (  "c0", 1 )
          self.c1  = SignalOut (  "c1", 1 )

          self.vdd = VddIn ( "vdd" )
          self.vss = VssIn ( "vss" )

        def Netlist ( self ) :
          Generate ( 'DpgenAdsb2f', 'adder_8'
                   , param = { 'nbit'     : 8
                             , 'physical' : True
                             }
                   )
          self.I = Inst ( 'adder_8', 'inst'
                        , map = { 'i0'      : self.in1
                                , 'i1'      : self.in2
                                , 'add_sub' : self.as
                                , 'q'       : self.out
                                , 'c30'     : self.c0
                                , 'c31'     : self.c1
                                , 'vdd'     : self.vdd
                                , 'vss'     : self.vss
                                }
                        )

        def Layout ( self ) :
          Place ( self.I, NOSYM, Ref(0, 0) )