# Oroshi - Analog Devices Layouts

- Main Page
- Related Pages
- Classes

- Class List
- Class Index
- Class Members

Public Member Functions | List of all members
RoutMatchedCapacitor Class Reference

Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix. More...

Inherits CapacitorUnit, CapacitorStack, and VerticalRoutingTracks.

## Public Member Functions
def | __init__
| A special method used to customize the class instance to an initial state in which : More...
def | route
| Draws the complete layout given the capacitor matrix. More...
def | setRules
| Defines technology rules used to draw the layout. More...
def | setLayers
| Defines all physical layers used to draw the layout. More...
def | computeDimensions
| Computes, through simple instructions and functions calls, layout variables detailed in Figure 2. More...
def | computeHRoutingTrackYCenter
| Computes centers' ordinates of the eight horizontal routing tracks. More...
def | computeHRLayerYCenter
| Sets the stretching value of top plates. More...
def | drawHRoutingTracks
| Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer `routingTracksLayer`. More...
def | drawHRLayers
| Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor . More...
def | drawCuts
| Draws all required cuts using physical layers : More...
def | drawOneCut_vRoutingTrack_HRLayer
| Draws one cut, in layer `cutLayer`, in order to connect a vertical routing track, at position `cutXMin` in metal 2, and a horizontal routing track, at position `cutYMin` in metal 3. More...
def | drawCuts_vRoutingTrack_hRoutingTrack
| Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3. More...
def | __stretchTopPlates__
| Iteratively performs top plates stretching for the capacitor matrix. More...
def | __stretchTopPlateCompactCap__
| Draws vertical stretched layers for a given elementary capacitor. More...
def | __setStretchingDySourceDyTarget__
| Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix. More...
def | __computeConnections__
| Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track. More...

## Detailed Description

Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix.

Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2 . Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions , the total number of vertical tracks is equivalent to couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.

Layout

An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.

## Constructor & Destructor Documentation

def __init__ | ( |  | self,
|  |  | vRTInstance
| ) |  |

A special method used to customize the class instance to an initial state in which :

- the class attirbutes describing positions and dimensions of the layout are computed in dedicated class methods,
- the attributes related to the capacitor matrix are copied from the `CapacitorStack` instance.

Position and dimensions attributes, also refered by layout variables, in Figure 2, are defined below :

Parameters

  device | The Hurricane AMS device onto which the layout is drawn.
  capacitorInstance | Instance of `CapacitorStack` class.
  capacitor | A nested list containing the matrix elements, which are `CapacitorUnit` objects.
  matchingScheme | A nested list, with equal dimensions as `capacitor` attribute, containing assignements of matrix elementary units to C1 and C2, identified by 1 and 2, respectively. Therefore, `self.matchingScheme` content is a succession of 1 and 2 values, defined as \ capacitor identifiers. For example, given a matrix of dimensions 2x2, the matching scheme can be . The first sub-list dictates that the first elementary capacitor, . The second element is affected to C2 and so on. An immediate and obvious consequence to this, is that an error is raised if `self.matchingSchem` and `self.capacitor` dimensions are not identical or if `self.matchingScheme` content is different from supported capacitor identifiers, '1' and '2'.
  capacitorType | Supported types of capacitors are MIM and PIP only. An exception is raised otherwise.
  abutmentBox | The matrix's abutment box.
  matrxiDim | The matrix dimensions, also equal to `self.matchingScheme` nested list dimensions.
  abutmentBox_spacing | The spacing between elementary units in the matrix. It is computed in `CapacitorStack` and is reloaded in `RoutMatchedCapacitor`. `self.abutmentBox_spacing` includes, vertical routing tracks width and minimum allowed spacing between two adjacent ones.
  hRoutingLayer_width | The width of horizontal routing layers in metal 2, which connect capacitors plates to vertical routing tracks.
  vRoutingTrack_width | The width of vertical routing tracks in metal 3, which connects identical nets together ( ie : bottom plates of C1, top plates of C2, bottom plates of C2 and top plates of C2 ).
  hRoutingTrack_width | The width of horizontal routing tracks in metal 2, which connect identical vertical routing tracks together.
  minSpacing_hRoutingTrack | Minimum spacing between horizontal routing tracks. Wide metal 2 specifications are considered since metal 2 dimensions may exceed 10 .

Remark:
  For more information about wide metal specifications, refer to ENG-183_rev8.pdf technology manual.

Parameters

  minimumPosition | The ordinate of the top plate's routing layer's bottom extremity after stretching.
  maximumPosition | The ordinate of the top plate's routing layer's top extremity, also equivalent to the top plate's top extremity.
  vRoutingTrackXCenter | A nested list of ordered dictionaries, with dimensions equal to `self.matrixDim`, containing abcissas of vertical routing tracks. All sub-lists' lengths are identical and are equal to 2. The first and second elements describe position of top plate track and bottom plate track, respectively. For example, given a matrix of dimensions 2x2, `self.vRoutingTrackXCenter` can be [[0, 2], [4,6], [8,10]] . Elements of this nested list have particular indexing as described in Figure 2.
  hRoutingtrackYCenter | A nested dictonary containing two keys, `topTracks` and `bottomTracks`. Each key contains as value a dictionary describing centers' ordinates of four parallel horizontal tracks. The reason why four tracks are needed on top and bottom positions of the matrix is that four nets are used, two for every capacitor `Ci`, were `i` is in [1,2].
  hRoutingLayerYCenter | A nested dicitonary containing two keys, `top` and `bottom`. Each key contains as value a dictionary describing centers' ordinates of horizontal routing layers.
  vRoutingTrackDict | A dictionary of routing tracks top and bottom extremities ordinates.
  topPlateStretching | Since not only the same metal 2 layer is used to draw top/bottom plates connections to vertical tracks but also the two plates are superimposed, the top plate's routing tracks is stretched. `self.topPlateStretching` is therefore the length added to top plate's routing layer in order to avoid short circuits between top and bottom plates routing to vertical tracks since the same metal is used for both.

References RoutMatchedCapacitor.capacitor, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, RoutMatchedCapacitor.dummyRingCapacitor, RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, RoutMatchedCapacitor.minimumPosition, RoutMatchedCapacitor.minSpacing_hRoutingTrack, RoutMatchedCapacitor.topPlateStretching, and RoutMatchedCapacitor.vRTInstance.

## Member Function Documentation

def route | ( |  | self,
|  |  | bbMode = `False`
| ) |  |

Draws the complete layout given the capacitor matrix.

`route` method is succession of calls to user-defined methods inside a newly created `Updatesession`. The following tasks are excecuted :

1. A nex `UpdateSession` is created,
2. all required physical layers are loaded,
3. technology rules are defined according to capacitor type,
4. layout dimension parameters are computed,
5. routing tracks and layers are drawn,
6. top plates are stretched,
7. all required cuts are drawn,
8. The `UpdateSession` is closed.

Meanwhile, an exception is raised when the entered `capacitor` is not a capacitor matrix or if the capacitor type is unsupported.

References RoutMatchedCapacitor.__stretchTopPlates__(), RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.computeDimensions(), CapacitorUnit.computeDimensions(), Stack.computeDimensions(), RoutMatchedCapacitor.drawCuts(), RoutMatchedCapacitor.drawDummyRing_hRTracks_Cuts(), RoutMatchedCapacitor.drawHRLayers(), RoutMatchedCapacitor.drawHRoutingTracks(), CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, RoutMatchedCapacitor.dummyRingCapacitor, VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, CapacitorUnit.metal3Width, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.nets, CapacitorStack.nets, RoutMatchedCapacitor.routeDummyRing(), RoutMatchedCapacitor.routeLeftAndRightSides(), RoutMatchedCapacitor.routeTopOrBottomSide(), RoutMatchedCapacitor.setLayers(), CapacitorStack.setRules(), CapacitorUnit.setRules(), RoutMatchedCapacitor.setRules(), CapacitorUnit.vpitch, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.

def setRules | ( |  | self | ) |

Defines technology rules used to draw the layout.

Some of the rules, namely those describing routing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.

Remark:
  All `CapacitorStack` class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported.

Returns
  a dictionary with rules labels as keys and rules content as values.

References CapacitorStack.capacitorType, CapacitorUnit.capacitorType, RoutMatchedCapacitor.capacitorType, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingLayer, RoutMatchedCapacitor.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, and RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut.

Referenced by RoutMatchedCapacitor.route(), and VerticalRoutingTracks.setRules().

def setLayers | ( |  | self | ) |

Defines all physical layers used to draw the layout.

Layers are loaded using `DataBase` API. The same routing layers are used for both capacitor types except cuts layers that connect top plates to vertical routing tracks. Basicaly, metal 2, meta 3, cut 1 and cut 2 are the ones defined.

Returns
  a dictionary composed of layers labels as keys and layers as values.

References CapacitorStack.capacitorType, CapacitorUnit.capacitorType, RoutMatchedCapacitor.capacitorType, CapacitorStack.dummyRing, and RoutMatchedCapacitor.dummyRing.

Referenced by RoutMatchedCapacitor.route().

def computeDimensions | ( |  | self,
|  |  | bbMode
| ) |  |

Computes, through simple instructions and functions calls, layout variables detailed in Figure 2.

References CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.abutmentBox_spacing, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, RoutMatchedCapacitor.computeBondingBoxDimInbbMode(), RoutMatchedCapacitor.computeHRLayerYCenter(), RoutMatchedCapacitor.computeHRoutingTrackYCenter(), RoutMatchedCapacitor.hRoutingLayer_width, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingLayer, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.vRoutingTrack_spacing, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackDict, and RoutMatchedCapacitor.vRoutingTrackXCenter.

Referenced by RoutMatchedCapacitor.route().

def computeHRoutingTrackYCenter | ( |  | self | ) |

Computes centers' ordinates of the eight horizontal routing tracks.

The tracks include four on top and four on bottom of the matrix. To do the computations, fist, center of the first bottom or top track, given in Figure 2, is computed. Then, all adjacent three centers are deduced by simples translation of the first one. Translation quantity is equal to the sum of distance between adjacent routing tracks, self.hRoutingTracks_spacing, and half width of the routing track itself, `self.hRoutingTrack_width`.

References RoutMatchedCapacitor.__setPlatesIds__(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingtrackYCenter, RoutMatchedCapacitor.maximumPosition, and RoutMatchedCapacitor.minimumPosition.

Referenced by RoutMatchedCapacitor.computeDimensions().

def computeHRLayerYCenter | ( |  | self | ) |

Sets the stretching value of top plates.

Then iteratively computes the centers of horizontal routing layer regarding top and bottom plates.

References RoutMatchedCapacitor.__findPossibleShortCircuits__(), VerticalRoutingTracks.__setStretching__(), RoutMatchedCapacitor.__setStretchingDySourceDyTarget__(), RoutMatchedCapacitor.bondingBox, RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.minSpacing_hRoutingLayer, RoutMatchedCapacitor.topPlateStretching, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.

Referenced by RoutMatchedCapacitor.computeDimensions().

def drawHRoutingTracks | ( |  | self,
|  |  | routingTracksLayer
| ) |  |

Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer `routingTracksLayer`.

References RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.nets, CapacitorStack.nets, and RoutMatchedCapacitor.vRoutingTrackXCenter.

Referenced by RoutMatchedCapacitor.route().

def drawHRLayers | ( |  | self,
|  |  | xPlateRLayer
| ) |  |

Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor .

References RoutMatchedCapacitor.__computeConnections__(), RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, and CapacitorStack.nets.

Referenced by RoutMatchedCapacitor.route().

def drawCuts | ( |  | self,
|  |  | layer_hRTrack_hRLayer,
|  |  | layer_tracksCut,
|  |  | layer_topPlateCut
| ) |  |

Draws all required cuts using physical layers :

- `layer_hRTrack_hRLayer` to connect bottom plates to vertical routing tracks,
- `layer_tracksCut` to connect vertical routing tracks to horizontal ones,
- `layer_topPlateCut` to connect top plates to vertical routing tracks. ALso in `drawCuts`, nUmber of maximum cuts number on every layer is computed and cuts enclosure is adjusted according to layer's width.

References RoutMatchedCapacitor.__setPlatesLabels__(), VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, RoutMatchedCapacitor.drawCuts_stretchedTopPlate(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_HRLayer(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack(), RoutMatchedCapacitor.drawOneCut_vRoutingTrack_HRLayer(), RoutMatchedCapacitor.hRoutingLayerYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.minWidth_vRoutingTrackCut, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.

Referenced by RoutMatchedCapacitor.route().

def drawOneCut_vRoutingTrack_HRLayer | ( |  | self,
|  |  | net,
|  |  | cutLayer,
|  |  | cutXMin,
|  |  | cutYMin,
|  |  | cutNumber
| ) |  |

Draws one cut, in layer `cutLayer`, in order to connect a vertical routing track, at position `cutXMin` in metal 2, and a horizontal routing track, at position `cutYMin` in metal 3.

References RoutMatchedCapacitor.minSpacing_hRoutingLayer_vRoutingTrack_cut, and VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut.

Referenced by RoutMatchedCapacitor.drawCuts().

def drawCuts_vRoutingTrack_hRoutingTrack | ( |  | self,
|  |  | cutLayer,
|  |  | cutNumber,
|  |  | enclosure_cut
| ) |  |

Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3.

References RoutMatchedCapacitor.__setPlatesIds__(), RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.dummyRingCapacitor, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.minWidth_vRoutingTrackCut, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.

Referenced by RoutMatchedCapacitor.drawCuts().

def __stretchTopPlates__ | ( |  | self,
|  |  | capacitor,
|  |  | rlayer
| ) |  |

Iteratively performs top plates stretching for the capacitor matrix.

Vertical segments are connected to top plate routing layer.

Parameters

  capacitor | Capacitor matrix.
  rlayer | Layer of the drawn vertical rectangle.

References RoutMatchedCapacitor.__stretchTopPlateCompactCap__(), VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, and CapacitorStack.nets.

Referenced by RoutMatchedCapacitor.route().

def __stretchTopPlateCompactCap__ | ( |  | self,
|  |  | net,
|  |  | capacitor,
|  |  | routingLayer,
|  |  | j = `0`
| ) |  |

Draws vertical stretched layers for a given elementary capacitor.

References RoutMatchedCapacitor.__setStretchingDySourceDyTarget__(), and RoutMatchedCapacitor.topPlateStretching.

Referenced by RoutMatchedCapacitor.__stretchTopPlates__().

def __setStretchingDySourceDyTarget__ | ( |  | self,
|  |  | capacitor,
|  |  | deltay
| ) |  |

Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix.

Parameters

  capacitor | .values() Elementary unit capacitor.
  deltay | Stretching value.

Returns
  A list that contains `dySource` and as top extremity and bottom extermity, respectively.

Referenced by RoutMatchedCapacitor.__stretchTopPlateCompactCap__(), and RoutMatchedCapacitor.computeHRLayerYCenter().

def __computeConnections__ | ( |  | self,
|  |  | i,
|  |  | j,
|  |  | capacitorIdentifier
| ) |  |

Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track.

Parameters

  (i,j) | row and column indexes, respectively, in the matrix which describe the elementary capacitor position in the matrix.
  capacitorIdentifier | equal to '1' if C1 and '2' if C2.

Returns
  A nested dicitionary. The overal dictionary is composed of keys equal to `topPlate` and bottomPlate and values equal to sub-dictionaries. The sub-dictionaries, are in their turn composed of two keys standing for the abcissa of the source and the abcissa of the target.

Remark:
  Naturally, an exception is raised if an unsupported capacitor identifier is given.

References RoutMatchedCapacitor.__findHRLDyTrarget__(), RoutMatchedCapacitor.__isCapacitorAdummy__(), RoutMatchedCapacitor.__setPlatesLabels__(), RoutMatchedCapacitor.capacitor, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, CapacitorStack.dummyElement, RoutMatchedCapacitor.dummyElement, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackXCenter, and RoutMatchedCapacitor.vRTsDistribution.

Referenced by RoutMatchedCapacitor.drawHRLayers().

The documentation for this class was generated from the following file:

- CapacitorRouted.py

Generated by doxygen 1.8.5 on Thu Mar 19 2020 | Return to top of page

Oroshi - Analog Devices Layouts | Copyright © 2018-2018 UPMC. All rights reserved