VerticalRoutingTracks(3)

NAME
VerticalRoutingTracks - Route two matched capacitors, C1 and C2, drawn in a capacitor matrix.

SYNOPSIS

Inherits CapacitorUnit, and CapacitorStack.

Inherited by RoutMatchedCapacitor.

  Public Member Functions
def __setStretching__ (self)
Sets vertical stretching value considering spacing between elementary capacitors in the matrix.
def setRules (self)
Defines technology rules used to draw the layout.
def drawVRoutingTracks (self, vRoutingTracksLayer)
Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer.

Detailed Description

Route two matched capacitors, C1 and C2, drawn in a capacitor matrix. Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2. Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routeing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.

Layout

An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.

Member Function Documentation

  def __setStretching__ ( self)

Sets vertical stretching value considering spacing between elementary capacitors in the matrix.

Returns:
    stratching value.

References CapacitorStack.abutmentBox_spacing.

Referenced by RoutMatchedCapacitor.computeHRLayerYCenter(), and VerticalRoutingTracks.drawVRoutingTracks().

  def setRules ( self)

Defines technology rules used to draw the layout. Some of the rules, namely those describing routeing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.

Remark: All CapacitorStack class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported.

Returns:
    a dictionary with rules labels as keys and rules content as values.

References VerticalRoutingTracks.capacitorInstance, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.computeVRTDimensions(), VerticalRoutingTracks.drawVRoutingTracks(), VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRTs(), VerticalRoutingTracks.minSpacing_hRoutingTrack, RoutMatchedCapacitor.minSpacing_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingLayer, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minWidth_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingTrackCut, and CapacitorUnit.setRules().

  def drawVRoutingTracks ( self, vRoutingTracksLayer)

Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer. Every elementary capacitor is consequently positioned between four routing tracks, two from each side. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in [1,2]. As given in Figure 2, capacitor $ C_{ij} $ with an even j value situated in even columns have and inversely for odd columns numbers.

References VerticalRoutingTracks.__computeVRTsNumber__(), VerticalRoutingTracks.__findCapIdsToEliminate__(), VerticalRoutingTracks.__findCapIdsToEliminatePerColumn__(), VerticalRoutingTracks.__findUsedCapIdsPerColumn__(), VerticalRoutingTracks.__findVRTsToEliminate__(), VerticalRoutingTracks.__setNetsDistribution__(), VerticalRoutingTracks.__setPlatesDistribution__(), VerticalRoutingTracks.__setStretching__(), VerticalRoutingTracks.__setVRTsDistribution__(), CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorInstance, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.computeXCenters(), CapacitorStack.dummyElement, CapacitorStack.dummyRing, VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingTrack_width, VerticalRoutingTracks.hRoutingTrack_width, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, RoutMatchedCapacitor.maximumPosition, VerticalRoutingTracks.maximumPosition, CapacitorUnit.metal2Width, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRT, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.nets, VerticalRoutingTracks.platesDistribution, CapacitorStack.vRoutingTrack_width, VerticalRoutingTracks.vRoutingTrackDict, RoutMatchedCapacitor.vRoutingTrackDict, VerticalRoutingTracks.vRoutingTrackXCenter, RoutMatchedCapacitor.vRoutingTrackXCenter, VerticalRoutingTracks.vRTsDistribution, RoutMatchedCapacitor.vRTsDistribution, and VerticalRoutingTracks.vRTsToEliminate.

Referenced by VerticalRoutingTracks.setRules().

Author

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