## march 2012

- A configuration file can be used to direct Stratus.
- A Stratus's description can now be exported either in Alliance VST format or standard VHDL using the `Save` method and the configuration file.
- A `Stimuli` method permits to generate stimuli for simulation.
- Thanks to the `Stimuli` method, a testbench can now automatically be generated either in Alliance PAT format or standard VHDL.
- The `Simul` method of the class `Model` permits to simulate either with the Alliance's simulator `asimut` or a standard VHDL simulator (`ghdl`).