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LEF/DEF 5.8 Language Reference

# Index

Symbols

,... in syntax
... in syntax
[] in syntax
{} in syntax
| in syntax
A
abutment pins
alias
expansion in DEF and LEF
names in DEF and LEF
statements in LEF and DEF
B
blockages, simplified
braces in syntax
brackets in syntax
BUSBITCHARS statement
description, DEF
C
capacitance
peripheral
wire-to-ground
cell modeling
combining blockages
characters
escape
information
COMPONENTS statement
description, DEF
conventions
user-defined arguments
user-entered text
COVER model, definition in LEF
D
database
converting LEF values to integer values
debugging
DEF files
LEF libraries
parametric macros
DEF
example
syntax overview
DEF syntax
PINS
DEF syntax and description
BUSBITCHARS
COMPONENTS
DESIGN
DIEAREA
DIVIDERCHAR
GCELLGRID
GROUPS
HISTORY
NETS
PINPROPERTIES
PROPERTYDEFINITIONS
REGIONS
ROW
SPECIALNETS
TECHNOLOGY
TRACKS
UNITS DISTANCE MICRONS
VERSION
VIAS
DESIGN statement
description, DEF
diagonal vias, recommendation for RGrid
DIEAREA statement
description, DEF
DIVIDERCHAR statement
description, DEF
E
edge capacitance
EEQ statement, LEF syntax
electrically equivalent models, LEF syntax
endcap models, definition in LEF
equivalent models
electrically equivalent (EEQ)
error checking, utilities
escape character
F
feedthrough pins
LEF
FOREIGN references
LEF syntax
offset between LEF and GDSII
G
GCell grid
restrictions
uniform, in DEF
GCELLGRID statement
description, DEF
GROUPS statement
description, DEF
H
HISTORY statement
description, DEF
I
INOUT pins, netlist
INPUT DEF command
error checking
INPUT GDSII command
with incremental LEF
INPUT LEF command
error checking
incremental capability
INPUT pins, netlist
italics in syntax
L
LAYER (nonrouting) statement
description, LEF
layers
for LEF via descriptions
routing order in LEF
LEF
example
files
distance precision
line length
overview
routing layer order
LEF syntax
overview
LEF syntax and description
LAYER, nonrouting
MACRO
NONDEFAULT rule
OBS, macro obstruction
PIN macro
PROPERTYDEFINITIONS
SITE
UNITS
VERSION
VIA
VIARULE
VIARULE viaRuleName GENERATE
LEF values converted to integer values
legal characters
library design, simplifying blockages
literal characters
M
macro obstruction, OBS statement
description, LEF
macro PIN statement
description, LEF
MACRO statement
description, LEF
models, site orientation
mustjoin pins
N
netlist pins
INOUT
INPUT
OUTPUT
nets
mustJoin nets
NETS statement
description, DEF
NONDEFAULT rule statement
description, LEF
O
OBS (macro obstruction) statement
description, LEF
obstructions, simplified
Or-bars in syntax
orientation
models
pin
OUTPUT pins, netlist
overlaps, specifying in LEF
P
peripheral capacitance
PIN (macro) statement
description, LEF
PINPROPERTIES statement
description, DEF
pins
abutment
direction in LEF
external, DEF
feedthrough pins in LEF
INOUT
INPUT
modeling in LEF
mustjoin
netlist
orientation
OUTPUT
power geometries
ring
using in LEF
PINS statement
syntax, DEF
PITCH parameter, ratio in three-layer design
placement site function, SITE statement in LEF
ports
in LEF
multiple pins
power pin
geometries in LEF
PROPERTYDEFINITIONS statement
description, DEF
description, LEF
R
REGIONS statement
description, DEF
regular wiring
orthogonal paths
RGrid, description
ring pins
routing time, diagonal vias
routing width, LEF syntax
ROW statement
description, DEF
S
scan chains
example
rules
SI units in LEF
SITE statement
description, LEF
sites
symmetry
special wiring
description
pins and wiring, DEF
SPECIALNETS statement
description, DEF
syntax conventions
T
TECHNOLOGY statement
description, DEF
three-layer design, pitch ratio
TRACKS statement
description, DEF
U
UNITS DISTANCE MICRONS statement
description, DEF
UNITS statement
description, LEF
V
values in library database
VERSION statement
description, DEF
vertical bars in syntax
VIA statement
description, LEF
VIARULE statement
description, LEF
VIARULE viaRuleName GENERATE statement
description, LEF
vias
default vias in LEF
layers for vias in LEF
VIAS statement
description, DEF
W
wide wire signal wire, specifying
wiring, regular
orthogonal paths
wiring, special
description
pins and wiring
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