# DpgenRam

- Name : DpgenRam - RAM Macro-Generator
- Synopsys :

      Generate ( 'DpgenRam', modelname
               , param = { 'nbit'     : n
                         , 'nword'    : regNumber
                         , 'physical' : True
                         }
               )

- Description : Generates a RAM of `regNumber` words of `n` bits named `modelname`.
- Terminal Names :
  - ck : clock signal (input, 1 bit)
  - w : write requested (input, 1 bit)
  - selram : select the write bus (input, 1 bit)
  - ad : the address (input, `Y` bits)
  - datain : write bus (input, `n` bits)
  - dataout : read bus (output, `n` bits)
  - vdd : power
  - vss : ground
- Parameters : Parameters are given in the map `param`.
  - nbit (mandatory) : Defines the size of the generator
  - nword (mandatory) : Defines the size of the words
  - physical (optional, default value : False) : In order to generate a layout
- Example :

      from stratus import *

      class inst_ram ( Model ) :

        def Interface ( self ) :
          self.ck      = SignalIn  (      "ck",  1 )
          self.w       = SignalIn  (       "w",  1 )
          self.selram  = SignalIn  (  "selram",  1 )
          self.ad      = SignalIn  (      "ad",  5 )
          self.datain  = SignalIn  (  "datain", 32 )
          self.dataout = TriState ( "dataout", 32 )

          self.vdd = VddIn ( "vdd" )
          self.vss = VssIn ( "vss" )

        def Netlist ( self ) :
          Generate ( 'DpgenRam', 'ram_32_32'
                   , param = { 'nbit'     : 32
                             , 'nword'    : 32
                             , 'physical' : True
                             }
                   )
          self.I = Inst ( 'ram_32_32', 'inst'
                        , map = { 'ck'      : self.ck
                                , 'w'       : self.w
                                , 'selram'  : self.selram
                                , 'ad'      : self.ad
                                , 'datain'  : self.datain
                                , 'dataout' : self.dataout
                                , 'vdd'     : self.vdd
                                , 'vss'     : self.vss
                                }
                        )

        def Layout ( self ) :
          Place ( self.I, NOSYM, Ref(0, 0) )