# DpgenFifo

- Name : DpgenFifo - Fifo Macro-Generator
- Synopsys :

      Generate ( 'DpgenFifo', modelname
               , param = { 'nbit'       : n
                         , 'nword'      : regNumber
                         , 'physical'   : True
                         }
               )

- Description : Generates a FIFO of `regNumber` words of `n` bits named `modelname`.
- Terminal Names :
  - ck : clock signal (input, 1 bit)
  - reset : reset signal (input, 1 bit)
  - r : read requested (input, 1 bit)
  - w : write requested (input, 1 bit)
  - rok : read acknowledge (output, 1 bit)
  - wok : write acknowledge (output, 1 bit)
  - sel : select the write bus (input, 1 bit)
  - datain0 : first write bus (input, `n` bits)
  - datain1 : second write bus (input, `n` bits)
  - dataout : read bus (output, `n` bits)
  - vdd : power
  - vss : ground
- Parameters : Parameters are given in the map `param`.
  - nbit (mandatory) : Defines the size of the words (even, between 2 and 64)
  - nword (mandatory) : Defines the number of words (even, between 4 and 32)
  - physical (optional, default value : False) : In order to generate a layout
- How it works :
  - datain0 and datain1 : the two write busses. Only one is used to actually write the FIFO, it is selected by the sel signal.
  - sel : when set to `zero` the datain0 is used to write the register word, otherwise it will be datain1.
  - r, rok : set r when a word is requested, rok tells that a word has effectively been popped (rok == not empty).
  - w, wok : set w when a word is pushed, wok tells that the word has effectively been pushed (wok == not full).
- Example :

      from stratus import *

      class inst_fifo ( Model ) :

        def Interface ( self ) :
          self.ck      = SignalIn    (       "ck", 1 )
          self.reset   = SignalIn    (    "reset", 1 )
          self.r       = SignalIn    (        "r", 1 )
          self.w       = SignalIn    (        "w", 1 )
          self.rok     = SignalInOut (      "rok", 1 )
          self.wok     = SignalInOut (      "wok", 1 )
          self.sel     = SignalIn    (      "sel", 1 )
          self.datain0 = SignalIn    (  "datain0", 4 )
          self.datain1 = SignalIn    (  "datain1", 4 )
          self.dataout = SignalOut   (  "dataout", 4 )

          self.vdd   = VddIn ( "vdd" )
          self.vss   = VssIn ( "vss" )

        def Netlist ( self ) :
          Generate ( 'DpgenFifo', 'fifo_4_16'
                   , param = { 'nbit'     : 4
                             , 'nword'    : 16
                             , 'physical' : True
                             }
                   )
          self.I = Inst ( 'fifo_4_16', 'inst'
                        , map = { 'ck'      : self.ck
                                , 'reset'   : self.reset
                                , 'r'       : self.r
                                , 'w'       : self.w
                                , 'rok'     : self.rok
                                , 'wok'     : self.wok
                                , 'sel'     : self.sel
                                , 'datain0' : self.datain0
                                , 'datain1' : self.datain1
                                , 'dataout' : self.dataout
                                , 'vdd'     : self.vdd
                                , 'vss'     : self.vss
                                }
                        )

        def Layout ( self ) :
          Place ( self.I, NOSYM, Ref(0, 0) )