542 lines
17 KiB
Verilog
542 lines
17 KiB
Verilog
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
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//Date : Fri Jan 26 19:13:14 2018
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//Host : LAPTOP-AKMF2NBQ running 64-bit major release (build 9200)
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//Command : generate_target system_wrapper.bd
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//Design : system_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module system_wrapper
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(DDR3_A14,
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DDR3_A15,
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DDR3_CKE1,
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DDR3_CLK1_N,
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DDR3_CLK1_P,
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DDR3_ODT1,
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DDR3_S1_B,
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SI5324_IN_clk_n,
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SI5324_IN_clk_p,
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SI5324_OUT_clk_n,
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SI5324_OUT_clk_p,
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SMA_OUT_clk_n,
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SMA_OUT_clk_p,
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SM_FAN_PWM,
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ULPI_clk,
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ULPI_data_io,
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ULPI_dir,
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ULPI_next,
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ULPI_rst,
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ULPI_stop,
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USER_CLOCK_IN_clk_n,
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USER_CLOCK_IN_clk_p,
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Vaux0_v_n,
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Vaux0_v_p,
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Vaux8_v_n,
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Vaux8_v_p,
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Vp_Vn_v_n,
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Vp_Vn_v_p,
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ddr3_sdram_addr,
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ddr3_sdram_ba,
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ddr3_sdram_cas_n,
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ddr3_sdram_ck_n,
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ddr3_sdram_ck_p,
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ddr3_sdram_cke,
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ddr3_sdram_cs_n,
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ddr3_sdram_dm,
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ddr3_sdram_dq,
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ddr3_sdram_dqs_n,
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ddr3_sdram_dqs_p,
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ddr3_sdram_odt,
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ddr3_sdram_ras_n,
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ddr3_sdram_reset_n,
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ddr3_sdram_we_n,
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dip_switches_8bits_tri_i,
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iic_main_scl_io,
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iic_main_sda_io,
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iic_mux_reset_b,
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lcd_7bits_tri_o,
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led_8bits_tri_o,
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linear_flash_addr,
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linear_flash_adv_ldn,
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linear_flash_ce_n,
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linear_flash_dq_io,
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linear_flash_oen,
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linear_flash_wen,
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mdio_mdc_mdc,
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mdio_mdc_mdio_io,
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phy_reset_out,
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push_buttons_5bits_tri_i,
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reset,
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rotary_switch_tri_i,
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rs232_uart_rxd,
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rs232_uart_txd,
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sgmii_mgt_clk_clk_n,
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sgmii_mgt_clk_clk_p,
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sgmii_rxn,
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sgmii_rxp,
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sgmii_txn,
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sgmii_txp,
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sys_diff_clock_clk_n,
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sys_diff_clock_clk_p);
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output [0:0]DDR3_A14;
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output [0:0]DDR3_A15;
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output [0:0]DDR3_CKE1;
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output [0:0]DDR3_CLK1_N;
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output [0:0]DDR3_CLK1_P;
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output [0:0]DDR3_ODT1;
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output [0:0]DDR3_S1_B;
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input SI5324_IN_clk_n;
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input SI5324_IN_clk_p;
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output SI5324_OUT_clk_n;
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output SI5324_OUT_clk_p;
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output SMA_OUT_clk_n;
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output SMA_OUT_clk_p;
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output [0:0]SM_FAN_PWM;
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input ULPI_clk;
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inout [7:0]ULPI_data_io;
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input ULPI_dir;
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input ULPI_next;
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output ULPI_rst;
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output ULPI_stop;
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input USER_CLOCK_IN_clk_n;
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input USER_CLOCK_IN_clk_p;
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input Vaux0_v_n;
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input Vaux0_v_p;
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input Vaux8_v_n;
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input Vaux8_v_p;
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input Vp_Vn_v_n;
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input Vp_Vn_v_p;
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output [13:0]ddr3_sdram_addr;
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output [2:0]ddr3_sdram_ba;
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output ddr3_sdram_cas_n;
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output [0:0]ddr3_sdram_ck_n;
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output [0:0]ddr3_sdram_ck_p;
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output [0:0]ddr3_sdram_cke;
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output [0:0]ddr3_sdram_cs_n;
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output [7:0]ddr3_sdram_dm;
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inout [63:0]ddr3_sdram_dq;
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inout [7:0]ddr3_sdram_dqs_n;
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inout [7:0]ddr3_sdram_dqs_p;
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output [0:0]ddr3_sdram_odt;
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output ddr3_sdram_ras_n;
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output ddr3_sdram_reset_n;
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output ddr3_sdram_we_n;
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input [7:0]dip_switches_8bits_tri_i;
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inout iic_main_scl_io;
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inout iic_main_sda_io;
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output [1:0]iic_mux_reset_b;
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output [6:0]lcd_7bits_tri_o;
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output [7:0]led_8bits_tri_o;
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output [26:1]linear_flash_addr;
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output linear_flash_adv_ldn;
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output linear_flash_ce_n;
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inout [15:0]linear_flash_dq_io;
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output linear_flash_oen;
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output linear_flash_wen;
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output mdio_mdc_mdc;
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inout mdio_mdc_mdio_io;
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output [0:0]phy_reset_out;
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input [4:0]push_buttons_5bits_tri_i;
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input reset;
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input [2:0]rotary_switch_tri_i;
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input rs232_uart_rxd;
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output rs232_uart_txd;
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input sgmii_mgt_clk_clk_n;
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input sgmii_mgt_clk_clk_p;
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input sgmii_rxn;
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input sgmii_rxp;
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output sgmii_txn;
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output sgmii_txp;
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input sys_diff_clock_clk_n;
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input sys_diff_clock_clk_p;
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wire [0:0]DDR3_A14;
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wire [0:0]DDR3_A15;
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wire [0:0]DDR3_CKE1;
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wire [0:0]DDR3_CLK1_N;
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wire [0:0]DDR3_CLK1_P;
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wire [0:0]DDR3_ODT1;
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wire [0:0]DDR3_S1_B;
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wire SI5324_IN_clk_n;
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wire SI5324_IN_clk_p;
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wire SI5324_OUT_clk_n;
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wire SI5324_OUT_clk_p;
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wire SMA_OUT_clk_n;
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wire SMA_OUT_clk_p;
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wire [0:0]SM_FAN_PWM;
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wire ULPI_clk;
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wire [0:0]ULPI_data_i_0;
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wire [1:1]ULPI_data_i_1;
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wire [2:2]ULPI_data_i_2;
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wire [3:3]ULPI_data_i_3;
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wire [4:4]ULPI_data_i_4;
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wire [5:5]ULPI_data_i_5;
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wire [6:6]ULPI_data_i_6;
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wire [7:7]ULPI_data_i_7;
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wire [0:0]ULPI_data_io_0;
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wire [1:1]ULPI_data_io_1;
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wire [2:2]ULPI_data_io_2;
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wire [3:3]ULPI_data_io_3;
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wire [4:4]ULPI_data_io_4;
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wire [5:5]ULPI_data_io_5;
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wire [6:6]ULPI_data_io_6;
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wire [7:7]ULPI_data_io_7;
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wire [0:0]ULPI_data_o_0;
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wire [1:1]ULPI_data_o_1;
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wire [2:2]ULPI_data_o_2;
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wire [3:3]ULPI_data_o_3;
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wire [4:4]ULPI_data_o_4;
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wire [5:5]ULPI_data_o_5;
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wire [6:6]ULPI_data_o_6;
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wire [7:7]ULPI_data_o_7;
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wire ULPI_data_t;
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wire ULPI_dir;
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wire ULPI_next;
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wire ULPI_rst;
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wire ULPI_stop;
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wire USER_CLOCK_IN_clk_n;
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wire USER_CLOCK_IN_clk_p;
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wire Vaux0_v_n;
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wire Vaux0_v_p;
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wire Vaux8_v_n;
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wire Vaux8_v_p;
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wire Vp_Vn_v_n;
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wire Vp_Vn_v_p;
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wire [13:0]ddr3_sdram_addr;
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wire [2:0]ddr3_sdram_ba;
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wire ddr3_sdram_cas_n;
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wire [0:0]ddr3_sdram_ck_n;
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wire [0:0]ddr3_sdram_ck_p;
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wire [0:0]ddr3_sdram_cke;
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wire [0:0]ddr3_sdram_cs_n;
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wire [7:0]ddr3_sdram_dm;
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wire [63:0]ddr3_sdram_dq;
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wire [7:0]ddr3_sdram_dqs_n;
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wire [7:0]ddr3_sdram_dqs_p;
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wire [0:0]ddr3_sdram_odt;
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wire ddr3_sdram_ras_n;
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wire ddr3_sdram_reset_n;
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wire ddr3_sdram_we_n;
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wire [7:0]dip_switches_8bits_tri_i;
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wire iic_main_scl_i;
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wire iic_main_scl_io;
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wire iic_main_scl_o;
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wire iic_main_scl_t;
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wire iic_main_sda_i;
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wire iic_main_sda_io;
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wire iic_main_sda_o;
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wire iic_main_sda_t;
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wire [1:0]iic_mux_reset_b;
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wire [6:0]lcd_7bits_tri_o;
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wire [7:0]led_8bits_tri_o;
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wire [26:1]linear_flash_addr;
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wire linear_flash_adv_ldn;
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wire linear_flash_ce_n;
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wire [0:0]linear_flash_dq_i_0;
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wire [1:1]linear_flash_dq_i_1;
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wire [10:10]linear_flash_dq_i_10;
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wire [11:11]linear_flash_dq_i_11;
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wire [12:12]linear_flash_dq_i_12;
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wire [13:13]linear_flash_dq_i_13;
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wire [14:14]linear_flash_dq_i_14;
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wire [15:15]linear_flash_dq_i_15;
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wire [2:2]linear_flash_dq_i_2;
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wire [3:3]linear_flash_dq_i_3;
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wire [4:4]linear_flash_dq_i_4;
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wire [5:5]linear_flash_dq_i_5;
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wire [6:6]linear_flash_dq_i_6;
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wire [7:7]linear_flash_dq_i_7;
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wire [8:8]linear_flash_dq_i_8;
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wire [9:9]linear_flash_dq_i_9;
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wire [0:0]linear_flash_dq_io_0;
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wire [1:1]linear_flash_dq_io_1;
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wire [10:10]linear_flash_dq_io_10;
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wire [11:11]linear_flash_dq_io_11;
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wire [12:12]linear_flash_dq_io_12;
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wire [13:13]linear_flash_dq_io_13;
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wire [14:14]linear_flash_dq_io_14;
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wire [15:15]linear_flash_dq_io_15;
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wire [2:2]linear_flash_dq_io_2;
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wire [3:3]linear_flash_dq_io_3;
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wire [4:4]linear_flash_dq_io_4;
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wire [5:5]linear_flash_dq_io_5;
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wire [6:6]linear_flash_dq_io_6;
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wire [7:7]linear_flash_dq_io_7;
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wire [8:8]linear_flash_dq_io_8;
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wire [9:9]linear_flash_dq_io_9;
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wire [0:0]linear_flash_dq_o_0;
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wire [1:1]linear_flash_dq_o_1;
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wire [10:10]linear_flash_dq_o_10;
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wire [11:11]linear_flash_dq_o_11;
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wire [12:12]linear_flash_dq_o_12;
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wire [13:13]linear_flash_dq_o_13;
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wire [14:14]linear_flash_dq_o_14;
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wire [15:15]linear_flash_dq_o_15;
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wire [2:2]linear_flash_dq_o_2;
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wire [3:3]linear_flash_dq_o_3;
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wire [4:4]linear_flash_dq_o_4;
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wire [5:5]linear_flash_dq_o_5;
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wire [6:6]linear_flash_dq_o_6;
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wire [7:7]linear_flash_dq_o_7;
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wire [8:8]linear_flash_dq_o_8;
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wire [9:9]linear_flash_dq_o_9;
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wire [0:0]linear_flash_dq_t_0;
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wire [1:1]linear_flash_dq_t_1;
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wire [10:10]linear_flash_dq_t_10;
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wire [11:11]linear_flash_dq_t_11;
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wire [12:12]linear_flash_dq_t_12;
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wire [13:13]linear_flash_dq_t_13;
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wire [14:14]linear_flash_dq_t_14;
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wire [15:15]linear_flash_dq_t_15;
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wire [2:2]linear_flash_dq_t_2;
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wire [3:3]linear_flash_dq_t_3;
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wire [4:4]linear_flash_dq_t_4;
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wire [5:5]linear_flash_dq_t_5;
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wire [6:6]linear_flash_dq_t_6;
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wire [7:7]linear_flash_dq_t_7;
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wire [8:8]linear_flash_dq_t_8;
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wire [9:9]linear_flash_dq_t_9;
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wire linear_flash_oen;
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wire linear_flash_wen;
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wire mdio_mdc_mdc;
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wire mdio_mdc_mdio_i;
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wire mdio_mdc_mdio_io;
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wire mdio_mdc_mdio_o;
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wire mdio_mdc_mdio_t;
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wire [0:0]phy_reset_out;
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wire [4:0]push_buttons_5bits_tri_i;
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wire reset;
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wire [2:0]rotary_switch_tri_i;
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wire rs232_uart_rxd;
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wire rs232_uart_txd;
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wire sgmii_mgt_clk_clk_n;
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wire sgmii_mgt_clk_clk_p;
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wire sgmii_rxn;
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wire sgmii_rxp;
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wire sgmii_txn;
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wire sgmii_txp;
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wire sys_diff_clock_clk_n;
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wire sys_diff_clock_clk_p;
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IOBUF ULPI_data_iobuf_0
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(.I(ULPI_data_o_0),
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.IO(ULPI_data_io[0]),
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.O(ULPI_data_i_0),
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.T(ULPI_data_t));
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IOBUF ULPI_data_iobuf_1
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(.I(ULPI_data_o_1),
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.IO(ULPI_data_io[1]),
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.O(ULPI_data_i_1),
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.T(ULPI_data_t));
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IOBUF ULPI_data_iobuf_2
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(.I(ULPI_data_o_2),
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.IO(ULPI_data_io[2]),
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.O(ULPI_data_i_2),
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.T(ULPI_data_t));
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IOBUF ULPI_data_iobuf_3
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(.I(ULPI_data_o_3),
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.IO(ULPI_data_io[3]),
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.O(ULPI_data_i_3),
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.T(ULPI_data_t));
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IOBUF ULPI_data_iobuf_4
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(.I(ULPI_data_o_4),
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.IO(ULPI_data_io[4]),
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.O(ULPI_data_i_4),
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.T(ULPI_data_t));
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IOBUF ULPI_data_iobuf_5
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(.I(ULPI_data_o_5),
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.IO(ULPI_data_io[5]),
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.O(ULPI_data_i_5),
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.T(ULPI_data_t));
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IOBUF ULPI_data_iobuf_6
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(.I(ULPI_data_o_6),
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.IO(ULPI_data_io[6]),
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.O(ULPI_data_i_6),
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.T(ULPI_data_t));
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IOBUF ULPI_data_iobuf_7
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(.I(ULPI_data_o_7),
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.IO(ULPI_data_io[7]),
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.O(ULPI_data_i_7),
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.T(ULPI_data_t));
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IOBUF iic_main_scl_iobuf
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(.I(iic_main_scl_o),
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.IO(iic_main_scl_io),
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.O(iic_main_scl_i),
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.T(iic_main_scl_t));
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IOBUF iic_main_sda_iobuf
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(.I(iic_main_sda_o),
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.IO(iic_main_sda_io),
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.O(iic_main_sda_i),
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.T(iic_main_sda_t));
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IOBUF linear_flash_dq_iobuf_0
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(.I(linear_flash_dq_o_0),
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.IO(linear_flash_dq_io[0]),
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.O(linear_flash_dq_i_0),
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.T(linear_flash_dq_t_0));
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IOBUF linear_flash_dq_iobuf_1
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(.I(linear_flash_dq_o_1),
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.IO(linear_flash_dq_io[1]),
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.O(linear_flash_dq_i_1),
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.T(linear_flash_dq_t_1));
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IOBUF linear_flash_dq_iobuf_10
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(.I(linear_flash_dq_o_10),
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.IO(linear_flash_dq_io[10]),
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.O(linear_flash_dq_i_10),
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.T(linear_flash_dq_t_10));
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IOBUF linear_flash_dq_iobuf_11
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(.I(linear_flash_dq_o_11),
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.IO(linear_flash_dq_io[11]),
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.O(linear_flash_dq_i_11),
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.T(linear_flash_dq_t_11));
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IOBUF linear_flash_dq_iobuf_12
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(.I(linear_flash_dq_o_12),
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.IO(linear_flash_dq_io[12]),
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.O(linear_flash_dq_i_12),
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.T(linear_flash_dq_t_12));
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IOBUF linear_flash_dq_iobuf_13
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(.I(linear_flash_dq_o_13),
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.IO(linear_flash_dq_io[13]),
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.O(linear_flash_dq_i_13),
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.T(linear_flash_dq_t_13));
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IOBUF linear_flash_dq_iobuf_14
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(.I(linear_flash_dq_o_14),
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.IO(linear_flash_dq_io[14]),
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.O(linear_flash_dq_i_14),
|
|
.T(linear_flash_dq_t_14));
|
|
IOBUF linear_flash_dq_iobuf_15
|
|
(.I(linear_flash_dq_o_15),
|
|
.IO(linear_flash_dq_io[15]),
|
|
.O(linear_flash_dq_i_15),
|
|
.T(linear_flash_dq_t_15));
|
|
IOBUF linear_flash_dq_iobuf_2
|
|
(.I(linear_flash_dq_o_2),
|
|
.IO(linear_flash_dq_io[2]),
|
|
.O(linear_flash_dq_i_2),
|
|
.T(linear_flash_dq_t_2));
|
|
IOBUF linear_flash_dq_iobuf_3
|
|
(.I(linear_flash_dq_o_3),
|
|
.IO(linear_flash_dq_io[3]),
|
|
.O(linear_flash_dq_i_3),
|
|
.T(linear_flash_dq_t_3));
|
|
IOBUF linear_flash_dq_iobuf_4
|
|
(.I(linear_flash_dq_o_4),
|
|
.IO(linear_flash_dq_io[4]),
|
|
.O(linear_flash_dq_i_4),
|
|
.T(linear_flash_dq_t_4));
|
|
IOBUF linear_flash_dq_iobuf_5
|
|
(.I(linear_flash_dq_o_5),
|
|
.IO(linear_flash_dq_io[5]),
|
|
.O(linear_flash_dq_i_5),
|
|
.T(linear_flash_dq_t_5));
|
|
IOBUF linear_flash_dq_iobuf_6
|
|
(.I(linear_flash_dq_o_6),
|
|
.IO(linear_flash_dq_io[6]),
|
|
.O(linear_flash_dq_i_6),
|
|
.T(linear_flash_dq_t_6));
|
|
IOBUF linear_flash_dq_iobuf_7
|
|
(.I(linear_flash_dq_o_7),
|
|
.IO(linear_flash_dq_io[7]),
|
|
.O(linear_flash_dq_i_7),
|
|
.T(linear_flash_dq_t_7));
|
|
IOBUF linear_flash_dq_iobuf_8
|
|
(.I(linear_flash_dq_o_8),
|
|
.IO(linear_flash_dq_io[8]),
|
|
.O(linear_flash_dq_i_8),
|
|
.T(linear_flash_dq_t_8));
|
|
IOBUF linear_flash_dq_iobuf_9
|
|
(.I(linear_flash_dq_o_9),
|
|
.IO(linear_flash_dq_io[9]),
|
|
.O(linear_flash_dq_i_9),
|
|
.T(linear_flash_dq_t_9));
|
|
IOBUF mdio_mdc_mdio_iobuf
|
|
(.I(mdio_mdc_mdio_o),
|
|
.IO(mdio_mdc_mdio_io),
|
|
.O(mdio_mdc_mdio_i),
|
|
.T(mdio_mdc_mdio_t));
|
|
system system_i
|
|
(.DDR3_A14(DDR3_A14),
|
|
.DDR3_A15(DDR3_A15),
|
|
.DDR3_CKE1(DDR3_CKE1),
|
|
.DDR3_CLK1_N(DDR3_CLK1_N),
|
|
.DDR3_CLK1_P(DDR3_CLK1_P),
|
|
.DDR3_ODT1(DDR3_ODT1),
|
|
.DDR3_S1_B(DDR3_S1_B),
|
|
.SI5324_IN_clk_n(SI5324_IN_clk_n),
|
|
.SI5324_IN_clk_p(SI5324_IN_clk_p),
|
|
.SI5324_OUT_clk_n(SI5324_OUT_clk_n),
|
|
.SI5324_OUT_clk_p(SI5324_OUT_clk_p),
|
|
.SMA_OUT_clk_n(SMA_OUT_clk_n),
|
|
.SMA_OUT_clk_p(SMA_OUT_clk_p),
|
|
.SM_FAN_PWM(SM_FAN_PWM),
|
|
.ULPI_clk(ULPI_clk),
|
|
.ULPI_data_i({ULPI_data_i_7,ULPI_data_i_6,ULPI_data_i_5,ULPI_data_i_4,ULPI_data_i_3,ULPI_data_i_2,ULPI_data_i_1,ULPI_data_i_0}),
|
|
.ULPI_data_o({ULPI_data_o_7,ULPI_data_o_6,ULPI_data_o_5,ULPI_data_o_4,ULPI_data_o_3,ULPI_data_o_2,ULPI_data_o_1,ULPI_data_o_0}),
|
|
.ULPI_data_t(ULPI_data_t),
|
|
.ULPI_dir(ULPI_dir),
|
|
.ULPI_next(ULPI_next),
|
|
.ULPI_rst(ULPI_rst),
|
|
.ULPI_stop(ULPI_stop),
|
|
.USER_CLOCK_IN_clk_n(USER_CLOCK_IN_clk_n),
|
|
.USER_CLOCK_IN_clk_p(USER_CLOCK_IN_clk_p),
|
|
.Vaux0_v_n(Vaux0_v_n),
|
|
.Vaux0_v_p(Vaux0_v_p),
|
|
.Vaux8_v_n(Vaux8_v_n),
|
|
.Vaux8_v_p(Vaux8_v_p),
|
|
.Vp_Vn_v_n(Vp_Vn_v_n),
|
|
.Vp_Vn_v_p(Vp_Vn_v_p),
|
|
.ddr3_sdram_addr(ddr3_sdram_addr),
|
|
.ddr3_sdram_ba(ddr3_sdram_ba),
|
|
.ddr3_sdram_cas_n(ddr3_sdram_cas_n),
|
|
.ddr3_sdram_ck_n(ddr3_sdram_ck_n),
|
|
.ddr3_sdram_ck_p(ddr3_sdram_ck_p),
|
|
.ddr3_sdram_cke(ddr3_sdram_cke),
|
|
.ddr3_sdram_cs_n(ddr3_sdram_cs_n),
|
|
.ddr3_sdram_dm(ddr3_sdram_dm),
|
|
.ddr3_sdram_dq(ddr3_sdram_dq),
|
|
.ddr3_sdram_dqs_n(ddr3_sdram_dqs_n),
|
|
.ddr3_sdram_dqs_p(ddr3_sdram_dqs_p),
|
|
.ddr3_sdram_odt(ddr3_sdram_odt),
|
|
.ddr3_sdram_ras_n(ddr3_sdram_ras_n),
|
|
.ddr3_sdram_reset_n(ddr3_sdram_reset_n),
|
|
.ddr3_sdram_we_n(ddr3_sdram_we_n),
|
|
.dip_switches_8bits_tri_i(dip_switches_8bits_tri_i),
|
|
.iic_main_scl_i(iic_main_scl_i),
|
|
.iic_main_scl_o(iic_main_scl_o),
|
|
.iic_main_scl_t(iic_main_scl_t),
|
|
.iic_main_sda_i(iic_main_sda_i),
|
|
.iic_main_sda_o(iic_main_sda_o),
|
|
.iic_main_sda_t(iic_main_sda_t),
|
|
.iic_mux_reset_b(iic_mux_reset_b),
|
|
.lcd_7bits_tri_o(lcd_7bits_tri_o),
|
|
.led_8bits_tri_o(led_8bits_tri_o),
|
|
.linear_flash_addr(linear_flash_addr),
|
|
.linear_flash_adv_ldn(linear_flash_adv_ldn),
|
|
.linear_flash_ce_n(linear_flash_ce_n),
|
|
.linear_flash_dq_i({linear_flash_dq_i_15,linear_flash_dq_i_14,linear_flash_dq_i_13,linear_flash_dq_i_12,linear_flash_dq_i_11,linear_flash_dq_i_10,linear_flash_dq_i_9,linear_flash_dq_i_8,linear_flash_dq_i_7,linear_flash_dq_i_6,linear_flash_dq_i_5,linear_flash_dq_i_4,linear_flash_dq_i_3,linear_flash_dq_i_2,linear_flash_dq_i_1,linear_flash_dq_i_0}),
|
|
.linear_flash_dq_o({linear_flash_dq_o_15,linear_flash_dq_o_14,linear_flash_dq_o_13,linear_flash_dq_o_12,linear_flash_dq_o_11,linear_flash_dq_o_10,linear_flash_dq_o_9,linear_flash_dq_o_8,linear_flash_dq_o_7,linear_flash_dq_o_6,linear_flash_dq_o_5,linear_flash_dq_o_4,linear_flash_dq_o_3,linear_flash_dq_o_2,linear_flash_dq_o_1,linear_flash_dq_o_0}),
|
|
.linear_flash_dq_t({linear_flash_dq_t_15,linear_flash_dq_t_14,linear_flash_dq_t_13,linear_flash_dq_t_12,linear_flash_dq_t_11,linear_flash_dq_t_10,linear_flash_dq_t_9,linear_flash_dq_t_8,linear_flash_dq_t_7,linear_flash_dq_t_6,linear_flash_dq_t_5,linear_flash_dq_t_4,linear_flash_dq_t_3,linear_flash_dq_t_2,linear_flash_dq_t_1,linear_flash_dq_t_0}),
|
|
.linear_flash_oen(linear_flash_oen),
|
|
.linear_flash_wen(linear_flash_wen),
|
|
.mdio_mdc_mdc(mdio_mdc_mdc),
|
|
.mdio_mdc_mdio_i(mdio_mdc_mdio_i),
|
|
.mdio_mdc_mdio_o(mdio_mdc_mdio_o),
|
|
.mdio_mdc_mdio_t(mdio_mdc_mdio_t),
|
|
.phy_reset_out(phy_reset_out),
|
|
.push_buttons_5bits_tri_i(push_buttons_5bits_tri_i),
|
|
.reset(reset),
|
|
.rotary_switch_tri_i(rotary_switch_tri_i),
|
|
.rs232_uart_rxd(rs232_uart_rxd),
|
|
.rs232_uart_txd(rs232_uart_txd),
|
|
.sgmii_mgt_clk_clk_n(sgmii_mgt_clk_clk_n),
|
|
.sgmii_mgt_clk_clk_p(sgmii_mgt_clk_clk_p),
|
|
.sgmii_rxn(sgmii_rxn),
|
|
.sgmii_rxp(sgmii_rxp),
|
|
.sgmii_txn(sgmii_txn),
|
|
.sgmii_txp(sgmii_txp),
|
|
.sys_diff_clock_clk_n(sys_diff_clock_clk_n),
|
|
.sys_diff_clock_clk_p(sys_diff_clock_clk_p));
|
|
endmodule
|