fix: Revert to manual reset for OpenOCD 0.12.0 compatibility
- The 'srst_assert_width' flag is not supported in 0.12.0. - Revert to using manual 'ftdi_set_signal' commands to pulse the nSRST line, which is the correct method for older OpenOCD versions. - This should fix both the syntax error and the 'mpsse_flush' timeouts.
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@ -1,4 +1,5 @@
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# OpenOCD Configuration to REBOOT a SiFive HiFive Pro P550 Board (v3)
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# OpenOCD Configuration to REBOOT a SiFive HiFive Pro P550 Board (v4)
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# Compatible with OpenOCD 0.12.0
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# ----------------------------------------------------------------
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# ----------------------------------------------------------------
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# 1. Adapter and Board Configuration
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# 1. Adapter and Board Configuration
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adapter driver ftdi
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adapter driver ftdi
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ftdi channel 2
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ftdi channel 2
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ftdi vid_pid 0x0403 0x6011
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ftdi vid_pid 0x0403 0x6011
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# NEW: Set the JTAG clock speed.
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# Start with a conservative but reasonable speed. 1000 kHz = 1 MHz.
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# If this works, you can try increasing it to 5000 or 10000 for faster performance.
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adapter speed 1000
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adapter speed 1000
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ftdi layout_init 0x0808 0x0a1b
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ftdi layout_init 0x0808 0x0a1b
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@ -33,23 +30,31 @@ target smp riscv.cpu0 riscv.cpu1 riscv.cpu2 riscv.cpu3
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# 3. Reset Configuration and Execution
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# 3. Reset Configuration and Execution
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# ----------------------------------------------------------------
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# ----------------------------------------------------------------
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# MODIFIED: Changed the reset configuration.
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# Configure the reset type, but without the unsupported timing flags.
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# By removing 'srst_pulls_trst', we are telling OpenOCD to handle the
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# We will control the pulse manually.
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# JTAG reset (nTRST) and the system reset (nSRST) as separate signals.
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reset_config srst_only
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# This is often more reliable on complex SoCs.
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reset_config srst_only srst_assert_width 100 srst_deassert_delay 100
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# Initialize OpenOCD and connect to the target
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# Initialize OpenOCD and connect to the target
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init
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init
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# --- The Improved Reboot Sequence ---
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# --- Manual Reboot Sequence for OpenOCD 0.12.0 ---
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# 'reset halt' asserts the reset line, then immediately halts the cores
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echo "!!! Manually asserting system reset (nSRST)..."
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# as they come out of reset, before they can execute any code.
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# Pull nSRST low (active low, so '0' asserts it)
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echo "!!! Issuing reset halt to gain control..."
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ftdi_set_signal nSRST 0
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reset halt
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# Hold the reset for 100ms to ensure the board registers it
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sleep 100
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# Now that the system is halted and stable, we can let it run.
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echo "!!! De-asserting system reset and attempting to halt..."
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echo "!!! Resuming execution to complete the reboot..."
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# Release nSRST (set it back to high-impedance/inactive)
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ftdi_set_signal nSRST 1
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# Wait a moment for the board to start coming out of reset
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sleep 100
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# Immediately after releasing reset, halt the cores.
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# This is the critical step to catch them before they boot the OS.
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halt
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echo "!!! System halted successfully. Resuming execution to boot..."
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resume
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resume
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# Exit OpenOCD
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# Exit OpenOCD
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