209 lines
8.0 KiB
ArmAsm
209 lines
8.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2018 by Andreas Bolsch *
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* andreas.bolsch@mni.thm.de *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m0
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.thumb
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.thumb_func
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/* Params:
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* r0 - total count (bytes), remaining bytes (out, 0 means successful)
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* r1 - flash page size
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* r2 - address offset into flash
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* r3 - OCTOSPI io_base
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* r8 - fifo start
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* r9 - fifo end + 1
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* Clobbered:
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* r4 - rp
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* r5 - address of OCTOSPI_DR
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* r6 - address of OCTOSPI_CCR
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* r7 - tmp
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* r10 - single 0x0 / dual 0x1
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*/
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#include "../../../../src/flash/nor/stmqspi.h"
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#define OCTOSPI_CCR_CCR (OCTOSPI_CCR - OCTOSPI_CCR)
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#define OCTOSPI_TCR_CCR (OCTOSPI_TCR - OCTOSPI_CCR)
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#define OCTOSPI_IR_CCR (OCTOSPI_IR - OCTOSPI_CCR)
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.macro octospi_abort
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movs r5, #(1<<SPI_ABORT) /* abort bit mask */
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ldr r7, [r3, #OCTOSPI_CR] /* get OCTOSPI CR register */
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orrs r7, r7, r5 /* set abort bit */
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str r7, [r3, #OCTOSPI_CR] /* store new CR register */
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.endm
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.macro wait_busy
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0:
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ldr r7, [r3, #OCTOSPI_SR] /* load status */
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lsrs r7, r7, #(SPI_BUSY+1) /* shift BUSY into C */
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bcs 0b /* loop until BUSY cleared */
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movs r7, #(1<<SPI_TCF) /* TCF bitmask */
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str r7, [r3, #OCTOSPI_FCR] /* clear TCF flag */
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.endm
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start:
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subs r0, r0, #1 /* decrement count for DLR */
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subs r1, r1, #1 /* page size mask and for DLR */
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ldr r4, rp /* load rp */
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ldr r7, [r3, #OCTOSPI_CR] /* get OCTOSPI_CR register */
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lsls r7, r7, #(31-SPI_DUAL_FLASH) /* clear higher order bits */
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lsrs r7, r7, #31 /* DUAL_FLASH bit into bit 0 */
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mov r10, r7 /* save in r10 */
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wip_loop:
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octospi_abort /* start in clean state */
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movs r5, #OCTOSPI_DR /* load OCTOSPI_DR address offset */
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adds r5, r5, r3 /* address of OCTOSPI_DR */
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movs r6, #OCTOSPI_CCR-OCTOSPI_DR /* load OCTOSPI_CCR address offset */
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adds r6, r6, r5 /* address of OCTOSPI_CCR */
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wait_busy
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ldr r7, cr_read_status /* indirect read mode */
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str r7, [r3, #OCTOSPI_CR] /* set mode */
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mov r7, r10 /* get dual bit */
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str r7, [r3, #OCTOSPI_DLR] /* one or two (for dual) bytes */
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ldr r7, ccr_read_status /* CCR for status read */
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str r7, [r6, #OCTOSPI_CCR_CCR] /* initiate status read */
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ldr r7, tcr_read_status /* TCR for status read */
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str r7, [r6, #OCTOSPI_TCR_CCR] /* instruction */
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ldr r7, ir_read_status /* IR for status read */
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str r7, [r6, #OCTOSPI_IR_CCR] /* instruction */
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movs r7, #0 /* dummy address */
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str r7, [r3, #OCTOSPI_AR] /* into AR (for 8-line mode) */
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ldrb r7, [r5] /* get first status register */
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lsrs r7, r7, #(SPIFLASH_BSY+1) /* if first flash busy, */
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bcs wip_loop /* then poll again */
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mov r7, r10 /* get dual bit */
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tst r7, r7 /* dual mode ? */
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beq write_enable /* not dual, then ok */
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ldrb r7, [r5] /* get second status register */
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lsrs r7, r7, #(SPIFLASH_BSY+1) /* if second flash busy, */
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bcs wip_loop /* then poll again */
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write_enable:
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tst r0, r0 /* test residual count */
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bmi exit /* if negative, then finished */
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wait_busy
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ldr r7, cr_write_enable /* indirect write mode */
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str r7, [r3, #OCTOSPI_CR] /* set mode */
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ldr r7, ccr_write_enable /* CCR for write enable */
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str r7, [r6, #OCTOSPI_CCR_CCR] /* initiate write enable */
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ldr r7, tcr_write_enable /* TCR for write enable */
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str r7, [r6, #OCTOSPI_TCR_CCR] /* write enable instruction */
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ldr r7, ir_write_enable /* IR for write enable */
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str r7, [r6, #OCTOSPI_IR_CCR] /* instruction */
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movs r7, #0 /* silicon bug in L5? dummy write */
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str r7, [r3, #OCTOSPI_AR] /* into AR resolves issue */
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wait_busy
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ldr r7, cr_read_status /* indirect read mode */
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str r7, [r3, #OCTOSPI_CR] /* set mode */
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mov r7, r10 /* get dual count */
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str r7, [r3, #OCTOSPI_DLR] /* one or two (for dual) bytes */
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ldr r7, ccr_read_status /* CCR for status read */
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str r7, [r6, #OCTOSPI_CCR_CCR] /* initiate status read */
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ldr r7, tcr_read_status /* TCR for status read */
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str r7, [r6, #OCTOSPI_TCR_CCR] /* instruction */
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ldr r7, ir_read_status /* IR for status read */
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str r7, [r6, #OCTOSPI_IR_CCR] /* instruction */
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movs r7, #0 /* dummy address */
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str r7, [r3, #OCTOSPI_AR] /* into AR (for 8-line mode) */
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ldrb r7, [r5] /* get first status register */
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lsrs r7, r7, #(SPIFLASH_WE+1) /* if first flash not */
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bcc error /* write enabled, then error */
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mov r7, r10 /* get dual bit */
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tst r7, r7 /* dual mode ? */
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beq start_write /* not dual, then ok */
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ldrb r7, [r5] /* get second status register */
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lsrs r7, r7, #(SPIFLASH_WE+1) /* if second flash not */
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bcc error /* write enabled, then error */
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start_write:
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wait_busy
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ldr r7, cr_page_write /* indirect write mode */
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str r7, [r3, #OCTOSPI_CR] /* set mode */
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mov r7, r2 /* get current start address */
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orrs r7, r7, r1 /* end of current page */
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subs r7, r7, r2 /* count-1 to end of page */
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cmp r7, r0 /* if this count <= remaining */
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bls write_dlr /* then write to end of page */
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mov r7, r0 /* else write all remaining */
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write_dlr:
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str r7, [r3, #OCTOSPI_DLR] /* size-1 in DLR register */
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ldr r7, ccr_page_write /* CCR for page write */
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str r7, [r6, #OCTOSPI_CCR_CCR] /* initiate transfer */
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ldr r7, tcr_page_write /* TCR for page write */
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str r7, [r6, #OCTOSPI_TCR_CCR] /* instruction */
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ldr r7, ir_page_write /* IR for page write */
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str r7, [r6, #OCTOSPI_IR_CCR] /* instruction */
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str r2, [r3, #OCTOSPI_AR] /* store SPI start address */
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write_loop:
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ldr r7, wp /* get wp */
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cmp r7, #0 /* if wp equals 0 */
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beq exit /* then abort */
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cmp r4, r7 /* check if fifo empty */
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beq write_loop /* wait until not empty */
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ldrb r7, [r4, #0] /* read next byte */
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strb r7, [r5] /* write next byte to DR */
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adds r4, r4, #1 /* increment internal rp */
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cmp r4, r9 /* internal rp beyond end? */
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blo upd_write /* if no, then ok */
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mov r4, r8 /* else wrap around */
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upd_write:
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adr r7, rp /* get address of rp */
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str r4, [r7] /* store updated rp */
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adds r2, r2, #1 /* increment address */
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subs r0, r0, #1 /* decrement (count-1) */
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bmi page_end /* stop if no data left */
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tst r2, r1 /* page end ? */
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bne write_loop /* if not, then next byte */
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page_end:
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ldr r7, [r3, #OCTOSPI_SR] /* load status */
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lsrs r7, r7, #(SPI_TCF+1) /* shift TCF into C */
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bcc page_end /* loop until TCF set */
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bal wip_loop /* then next page */
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error:
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movs r0, #0 /* return 0xFFFFFFFF */
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subs r0, r0, #2 /* for error */
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exit:
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adds r0, r0, #1 /* increment count due to the -1 */
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octospi_abort /* to idle state */
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.align 2 /* align to word, bkpt is 4 words */
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bkpt #0 /* before code end for exit_point */
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.align 2 /* align to word */
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cr_read_status:
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.space 4 /* OCTOSPI_CR value for READ_STATUS command */
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ccr_read_status:
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.space 4 /* OCTOSPI_CCR value for READ_STATUS command */
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tcr_read_status:
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.space 4 /* OCTOSPI_TCR value for READ_STATUS command */
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ir_read_status:
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.space 4 /* OCTOSPI_IR value for READ_STATUS command */
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cr_write_enable:
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.space 4 /* OCTOSPI_CR value for WRITE_ENABLE command */
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ccr_write_enable:
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.space 4 /* OCTOSPI_CCR value for WRITE_ENABLE command */
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tcr_write_enable:
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.space 4 /* OCTOSPI_TCR value for WRITE_ENABLE command */
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ir_write_enable:
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.space 4 /* OCTOSPI_IR value for WRITE_ENABLE command */
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cr_page_write:
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.space 4 /* OCTOSPI_CR value for PAGE_PROG command */
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ccr_page_write:
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.space 4 /* OCTOSPI_CCR value for PAGE_PROG command */
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tcr_page_write:
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.space 4 /* OCTOSPI_TCR value for PAGE_PROG command */
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ir_page_write:
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.space 4 /* OCTOSPI_IR value for PAGE_PROG command */
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.equ wp, . /* wp, uint32_t */
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.equ rp, wp + 4 /* rp, uint32_t */
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.equ buffer, rp + 4 /* buffer follows right away */
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