129 lines
4.3 KiB
C
129 lines
4.3 KiB
C
/***************************************************************************
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* Copyright (C) 2005, 2006 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2007,2008 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_EMBEDDEDICE_H
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#define OPENOCD_TARGET_EMBEDDEDICE_H
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#include "arm7_9_common.h"
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enum {
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EICE_DBG_CTRL = 0,
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EICE_DBG_STAT = 1,
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EICE_COMMS_CTRL = 2,
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EICE_COMMS_DATA = 3,
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EICE_W0_ADDR_VALUE = 4,
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EICE_W0_ADDR_MASK = 5,
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EICE_W0_DATA_VALUE = 6,
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EICE_W0_DATA_MASK = 7,
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EICE_W0_CONTROL_VALUE = 8,
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EICE_W0_CONTROL_MASK = 9,
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EICE_W1_ADDR_VALUE = 10,
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EICE_W1_ADDR_MASK = 11,
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EICE_W1_DATA_VALUE = 12,
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EICE_W1_DATA_MASK = 13,
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EICE_W1_CONTROL_VALUE = 14,
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EICE_W1_CONTROL_MASK = 15,
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EICE_VEC_CATCH = 16
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};
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enum {
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EICE_DBG_CONTROL_ICEDIS = 5,
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EICE_DBG_CONTROL_MONEN = 4,
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EICE_DBG_CONTROL_INTDIS = 2,
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EICE_DBG_CONTROL_DBGRQ = 1,
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EICE_DBG_CONTROL_DBGACK = 0,
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};
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enum {
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EICE_DBG_STATUS_IJBIT = 5,
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EICE_DBG_STATUS_ITBIT = 4,
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EICE_DBG_STATUS_SYSCOMP = 3,
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EICE_DBG_STATUS_IFEN = 2,
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EICE_DBG_STATUS_DBGRQ = 1,
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EICE_DBG_STATUS_DBGACK = 0
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};
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enum {
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EICE_W_CTRL_ENABLE = 0x100,
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EICE_W_CTRL_RANGE = 0x80,
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EICE_W_CTRL_CHAIN = 0x40,
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EICE_W_CTRL_EXTERN = 0x20,
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EICE_W_CTRL_nTRANS = 0x10,
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EICE_W_CTRL_nOPC = 0x8,
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EICE_W_CTRL_MAS = 0x6,
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EICE_W_CTRL_ITBIT = 0x2,
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EICE_W_CTRL_nRW = 0x1
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};
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enum {
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EICE_COMM_CTRL_WBIT = 1,
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EICE_COMM_CTRL_RBIT = 0
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};
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struct embeddedice_reg {
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int addr;
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struct arm_jtag *jtag_info;
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};
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struct reg_cache *embeddedice_build_reg_cache(struct target *target,
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struct arm7_9_common *arm7_9);
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int embeddedice_setup(struct target *target);
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int embeddedice_read_reg(struct reg *reg);
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int embeddedice_read_reg_w_check(struct reg *reg,
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uint8_t *check_value, uint8_t *check_mask);
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void embeddedice_write_reg(struct reg *reg, uint32_t value);
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void embeddedice_store_reg(struct reg *reg);
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void embeddedice_set_reg(struct reg *reg, uint32_t value);
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int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
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int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
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int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout);
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/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be
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* this faster version of embeddedice_write_reg
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*/
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static inline void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value)
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{
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uint8_t out_reg_addr = (1 << 5) | reg_addr;
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uint8_t out_value[4];
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buf_set_u32(out_value, 0, 32, value);
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struct scan_field fields[2] = {
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{ .num_bits = 32, .out_value = out_value },
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{ .num_bits = 6, .out_value = &out_reg_addr },
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};
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jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
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}
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void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer,
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int little, int count);
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#endif /* OPENOCD_TARGET_EMBEDDEDICE_H */
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