60 lines
1.7 KiB
INI
60 lines
1.7 KiB
INI
# Freescale i.MX6 series single/dual/quad core processor
|
|
|
|
if { [info exists CHIPNAME] } {
|
|
set _CHIPNAME $CHIPNAME
|
|
} else {
|
|
set _CHIPNAME imx6
|
|
}
|
|
|
|
# CoreSight Debug Access Port
|
|
if { [info exists DAP_TAPID] } {
|
|
set _DAP_TAPID $DAP_TAPID
|
|
} else {
|
|
set _DAP_TAPID 0x4ba00477
|
|
}
|
|
|
|
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
|
|
-expected-id $_DAP_TAPID
|
|
|
|
# SDMA / no IDCODE
|
|
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
|
|
|
|
# System JTAG Controller
|
|
if { [info exists SJC_TAPID] } {
|
|
set _SJC_TAPID $SJC_TAPID
|
|
} else {
|
|
set _SJC_TAPID 0x0191c01d
|
|
}
|
|
set _SJC_TAPID2 0x2191c01d
|
|
set _SJC_TAPID3 0x2191e01d
|
|
set _SJC_TAPID4 0x1191c01d
|
|
|
|
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
|
|
-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
|
|
-expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
|
|
|
|
# GDB target: Cortex-A9, using DAP, configuring only one core
|
|
# Base addresses of cores:
|
|
# core 0 - 0x82150000
|
|
# core 1 - 0x82152000
|
|
# core 2 - 0x82154000
|
|
# core 3 - 0x82156000
|
|
set _TARGETNAME $_CHIPNAME.cpu.0
|
|
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
|
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
|
|
-coreid 0 -dbgbase 0x82150000
|
|
|
|
# some TCK cycles are required to activate the DEBUG power domain
|
|
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
|
|
|
|
proc imx6_dbginit {target} {
|
|
# General Cortex-A8/A9 debug initialisation
|
|
cortex_a dbginit
|
|
}
|
|
|
|
# Slow speed to be sure it will work
|
|
adapter_khz 1000
|
|
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
|
|
|
|
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
|