74 lines
2.4 KiB
INI
74 lines
2.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# This is the config for an Allwinner V3/V3s (sun8iw8).
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#
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# Notes:
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# - Single core ARM Cortex-A7 with a maximum frequency of 1.2 GHz.
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# - Thumb-2 Technology
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# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction
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# for acceleration of media and signal processing functions
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# - Support Large Physical Address Extensions(LPAE)
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# - VFPv4 Floating Point Unit
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# - 32KB L1 Instruction cache and 32KB L1 Data cache
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# - 128KB L2 cache
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# - has some integrated DDR2 RAM.
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#
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# Pins related for debug and bootstrap:
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# JTAG
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# JTAG_TMS PF0, SDC0_D1
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# JTAG_TDI PF1, SDC0_D0
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# JTAG_TDO PF3, SDC0_CMD
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# JTAG_TCK PF5, SDC0_D2
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# UART
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# None of UART ports seems to be enabled by ROM.
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# UART0_TX PF2, SDC0_CLK Per default disabled
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# UART0_RX PF4, SDC0_D3 Per default disabled
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# UART1_TX PE21 Per default disabled
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# UART1_RX PE22 Per default disabled
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# UART2_TX PB0 Per default disabled
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# UART2_RX PB1 Per default disabled
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#
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# JTAG is enabled by default after power-on on listed JTAG_* pins. So far the
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# boot sequence is:
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# Time Action
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# 0000ms Power ON
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# 0200ms JTAG enabled
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# 0220ms JTAG pins switched to SD mode
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#
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# The time frame of 20ms can be not enough to init and halt the CPU. In this
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# case I would recommend to set: "adapter speed 15000"
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# To get more or less precise timings, the board should provide reset pin,
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# or some bench power supply with remote function. In my case I used
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# EEZ H24005 with this command to power on and halt the target:
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# "exec echo "*TRG" > /dev/ttyACM0; sleep 220; reset halt"
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# After this it is possible to enable JTAG mode again from boot loader or OS.
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# Following DAPs are available:
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# dap[0]->MEM-AP AHB
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# dap[1]->MEM-AP APB->CA7[0]
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME v3s
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}
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x5ba00477
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}
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# No NRST or SRST is present on the SoC. Boards may provide
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# some sort of Power cycle reset for complete board or SoC.
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# For this case we provide srst_pulls_trst so the board config
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# only needs to set srst_only.
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reset_config none srst_pulls_trst
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
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-expected-id $_DAP_TAPID
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# Add Cortex A7 core
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
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