148 lines
3.7 KiB
INI
148 lines
3.7 KiB
INI
# DM365 EVM board -- Beta
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# http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
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# http://support.spectrumdigital.com/boards/evmdm365
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source [find target/ti_dm365.cfg]
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# NOTE: in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
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# connector, so it doesn't affect generation of the reset signal.
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# Accordingly, resets require something else. ICEpick could do it;
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# but its docs aren't generally available.
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#
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# At this writing, newer boards aren't available ... so assume no SRST.
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# Also ICEpick docs aren't available ... so we must use watchdog reset,
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# and hope the CPU isn't wedged or in a WFI loop (either of which can
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# block access to CPU and thus watchdog registers).
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reset_config trst_only
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$_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
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# SW5.1 routes CS0: NAND vs OneNAND.
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# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
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# for boot-from-flash, those must agree with SW4.3:1 settings.
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if { [info exists CS0MODE] } {
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# NAND or OneNAND
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set CS0 $CS0MODE
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} else {
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set CS0 ""
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echo "WARNING: CS0 configuration not known"
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proc cs0_setup {a_emif} {}
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proc flashprobe {} {}
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}
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set a_emif [dict get $dm365 a_emif]
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# As shipped: boot from NAND.
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if { $CS0 == "NAND" } {
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echo "CS0 NAND"
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# NAND socket has two chipselects. Default MT29F16G08FAA chip
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# has 1GByte on each one.
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# NOTE: "hwecc4" here presumes that you're not updating anything
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# that needs infix layout (e.g. UBL, old U-Boot, etc)
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nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
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nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
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proc cs0_setup {a_emif} {
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global dm365
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# 8 bit EMIF
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davinci_pinmux $dm365 2 0x00000016
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# slow/pessimistic timings
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set nand_timings 0x40400204
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# fast (25% faster page reads)
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#set nand_timings 0x0400008c
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# CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
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mww [expr $a_emif + 0x10] $nand_timings
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# NANDFCR -- CS0 has NAND
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mww [expr $a_emif + 0x60] 0x01
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}
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proc flashprobe {} {
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nand probe 0
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nand probe 1
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}
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} elseif { $CS0 == "OneNAND" } {
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echo "CS0 OneNAND"
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# No support for this OneNAND in OpenOCD (yet) or Linux ...
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# REVISIT OneNAND timings not verified to work!
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echo "WARNING -- OneNAND not yet tested!"
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proc cs0_setup {a_emif} {
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global dm365
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# 16 bit EMIF
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davinci_pinmux $dm365 2 0x00000055
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# CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
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mww [expr $a_emif + 0x10] 0x00000001
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# ONENANDCTRL -- CS0 has OneNAND, enable sync reads
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mww [expr $a_emif + 0x5c] 0x0441
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}
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proc flashprobe {} { }
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}
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# NOTE: disable or replace this call to dm365evm_init if you're
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# debugging new UBL/NANDboot code from SRAM.
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$_TARGETNAME configure -event reset-init { dm365evm_init }
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#
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# This post-reset init is called when the MMU isn't active, all IRQs
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# are disabled, etc. It should do most of what a UBL does, except for
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# loading code (like U-Boot) into DRAM and running it.
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#
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proc dm365evm_init {} {
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global dm365
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echo "Initialize DM365 EVM board"
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# CLKIN = 24 MHz ... can't talk quickly to ARM yet
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adapter speed 1500
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# FIXME -- PLL init
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########################
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# PINMUX setup
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davinci_pinmux $dm365 0 0x00fd0000
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davinci_pinmux $dm365 1 0x00145555
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# mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
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davinci_pinmux $dm365 3 0x375affff
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davinci_pinmux $dm365 4 0x55556555
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########################
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# PSC setup (minimal)
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# DDR EMIF/13, AEMIF/14, UART0/19
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psc_enable 13
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psc_enable 14
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psc_enable 19
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psc_go
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# FIXME setup DDR2 (needs PLL)
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########################
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# ASYNC EMIF
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set a_emif [dict get $dm365 a_emif]
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# AWCCR
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mww [expr $a_emif + 0x04] 0xff
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# CS0 == NAND or OneNAND
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cs0_setup $a_emif
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# CS1 == CPLD
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mww [expr $a_emif + 0x14] 0x00a00505
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# FIXME setup UART0
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flashprobe
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}
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