324 lines
11 KiB
Tcl
324 lines
11 KiB
Tcl
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# board(-config) specfic parameters file.
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# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
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proc config {label} {
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return [dict get [configC100] $label ]
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}
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# show the value for the param. with label
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proc showconfig {label} {
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puts [format "0x%x" [dict get [configC100] $label ]]
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}
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# Telo board config
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# when there are more then one board config
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# use soft links to c100board-config.tcl
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# so that only the right board-config gets
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# included (just like include/configs/board-configs.h
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# in u-boot.
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proc configC100 {} {
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# xtal freq. 24MHz
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dict set configC100 CFG_REFCLKFREQ 24000000
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# Amba Clk 165MHz
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dict set configC100 CONFIG_SYS_HZ_CLOCK 165000000
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dict set configC100 w_amba 1
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dict set configC100 x_amba 1
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# y = amba_clk * (w+1)*(x+1)*2/xtal_clk
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dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
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# Arm Clk 450MHz, must be a multiple of 25 MHz
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dict set configC100 CFG_ARM_CLOCK 450000000
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dict set configC100 w_arm 0
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dict set configC100 x_arm 1
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# y = arm_clk * (w+1)*(x+1)*2/xtal_clk
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dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
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}
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proc setupNOR {} {
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puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
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# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
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set EX_CSEN_REG [regs EX_CSEN_REG ]
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set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
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set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
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set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
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set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
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set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
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set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
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set EX_MFSM_REG [regs EX_MFSM_REG ]
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set EX_CSFSM_REG [regs EX_CSFSM_REG ]
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set EX_WRFSM_REG [regs EX_WRFSM_REG ]
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set EX_RDFSM_REG [regs EX_RDFSM_REG ]
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# enable Expansion Bus Clock + CS0 (NOR)
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mww $EX_CSEN_REG 0x3
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# set the address space for CS0=16MB
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mww $EX_CS0_SEG_REG 0x7ff
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# set the CS0 bus width to 16-bit
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mww $EX_CS0_CFG_REG 0x202
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# set timings to NOR
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mww $EX_CS0_TMG1_REG 0x03034006
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mww $EX_CS0_TMG2_REG 0x04040002
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#mww $EX_CS0_TMG3_REG
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# set EBUS clock 165/5=33MHz
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mww $EX_CLOCK_DIV_REG 0x5
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# everthing else is OK with default
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}
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proc bootNOR {} {
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
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set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
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set DDR_RST [regs DDR_RST]
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# put DDR controller in reset (so that it comes reset in u-boot)
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mmw $BLOCK_RESET_REG 0x0 $DDR_RST
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# setup CS0 controller for NOR
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setupNOR
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# make sure we are accessing the lower part of NOR
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lowGPIO5
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# set PC to start of NOR (at boot 0x20000000 = 0x0)
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reg pc $EXP_CS0_BASEADDR
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# run
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resume
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}
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proc setupGPIO {} {
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puts "Setting up GPIO block for Telo"
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# This is current setup for Telo (see sch. for details):
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#GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
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#GPIO1 irq line for FXS-FXO
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#GPIO5 addr22 for NOR flash (access to upper 8MB)
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#GPIO17 reset for DECT module.
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#GPIO29 CS_n for NAND
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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set GPIO_OE_REG [regs GPIO_OE_REG]
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# set GPIO29=GPIO17=1, GPIO5=0
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mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
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# enable [as output] GPIO29,GPIO17,GPIO5
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mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5]
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}
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proc highGPIO5 {} {
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puts "GPIO5 high"
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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# set GPIO5=1
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mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
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}
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proc lowGPIO5 {} {
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puts "GPIO5 low"
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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# set GPIO5=0
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mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
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}
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proc boardID {id} {
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# so far built:
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# 4'b1111
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dict set boardID 15 name "EVT1"
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dict set boardID 15 ddr2size 128M
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# dict set boardID 15 nandsize 1G
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# dict set boardID 15 norsize 16M
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# 4'b0000
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dict set boardID 0 name "EVT2"
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dict set boardID 0 ddr2size 128M
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# 4'b0001
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dict set boardID 1 name "EVT3"
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dict set boardID 1 ddr2size 256M
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# 4'b1110
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dict set boardID 14 name "EVT3_old"
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dict set boardID 14 ddr2size 128M
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# 4'b0010
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dict set boardID 2 name "EVT4"
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dict set boardID 2 ddr2size 256M
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return $boardID
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}
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# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
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# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
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proc ooma_board_detect {} {
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set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
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# read the current value of the BOOTSRAP pins
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set tmp [mrw $GPIO_BOOTSTRAP_REG]
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puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
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# extract the GPBP bits
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set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
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# display board ID
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puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
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# return the ddr2 size, used to configure DDR2 on a given board.
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return [dict get [boardID $gpbt] $gpbt ddr2size]
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}
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proc configureDDR2regs_256M {} {
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puts "ConfigureDDR2regs_256M TBD"
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}
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# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
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# The values are computed based on Mindspeed and Nanya datasheets
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proc configureDDR2regs_128M {} {
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set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
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set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
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set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
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set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
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set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
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set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
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set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
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set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
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set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
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set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
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set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
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set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
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set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
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set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
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set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
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set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
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set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
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set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
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set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
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set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
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set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
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set DENALI_CTL_02_VAL 0x0100010000010100
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set DENALI_CTL_11_VAL 0x433A42124A650A37
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# set some default values
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mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
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mw64bit $DENALI_CTL_01_DATA 0x0100000100000101
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mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
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mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
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mw64bit $DENALI_CTL_04_DATA 0x0201010100000201
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mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
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mw64bit $DENALI_CTL_06_DATA 0x050A020200020202
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mw64bit $DENALI_CTL_07_DATA 0x000000030E0B0205
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mw64bit $DENALI_CTL_08_DATA 0x6427003F3F0A0209
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mw64bit $DENALI_CTL_09_DATA 0x1A00002F00001A00
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mw64bit $DENALI_CTL_10_DATA 0x01202020201A1A1A
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mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
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mw64bit $DENALI_CTL_12_DATA 0x0000080000000800
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mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
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mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
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mw64bit $DENALI_CTL_15_DATA 0x0508000000000000
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mw64bit $DENALI_CTL_16_DATA 0x000020472D200000
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mw64bit $DENALI_CTL_17_DATA 0x0000000008000000
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mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
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mw64bit $DENALI_CTL_19_DATA 0x00001400C8030604
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mw64bit $DENALI_CTL_20_DATA 0x00000000823600C8
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set wr_dqs_shift 0x40
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# start DDRC
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mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
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# wait int_status[2] (DRAM init complete)
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puts -nonewline "Waiting for DDR2 controller to init..."
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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while { [expr $tmp & 0x040000] == 0 } {
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sleep 1
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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}
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mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
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puts "done."
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# do ddr2 training sequence
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# TBD (for now, if you need it, run trainDDR command)
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}
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proc setupUART0 {} {
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# configure UART0 to 115200, 8N1
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set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
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set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
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set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
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set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0]
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set UART0_LCR [regs UART0_LCR]
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set LCR_DLAB [regs LCR_DLAB]
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set UART0_DLL [regs UART0_DLL]
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set UART0_DLH [regs UART0_DLH]
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set UART0_IIR [regs UART0_IIR]
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set UART0_IER [regs UART0_IER]
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set LCR_ONE_STOP [regs LCR_ONE_STOP]
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set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
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set FCR_XMITRES [regs FCR_XMITRES]
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set FCR_RCVRRES [regs FCR_RCVRRES]
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set FCR_FIFOEN [regs FCR_FIFOEN]
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set IER_UUE [regs IER_UUE]
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# unlock writing to IOCTRL register
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mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
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# enable UART0
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mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
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# baudrate 115200
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# This should really be amba_clk/(16*115200) but amba_clk=165MHz
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set tmp 89
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# Enable Divisor Latch access
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mmw $UART0_LCR $LCR_DLAB 0x0
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# set the divisor to $tmp
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mww $UART0_DLL [expr $tmp & 0xff]
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mww $UART0_DLH [expr $tmp >> 8]
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# Disable Divisor Latch access
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mmw $UART0_LCR 0x0 $LCR_DLAB
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# set the UART to 8N1
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mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0
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# reset FIFO
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mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0
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# enable FFUART
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mww $UART0_IER $IER_UUE
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}
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proc putcUART0 {char} {
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set UART0_LSR [regs UART0_LSR]
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set UART0_THR [regs UART0_THR]
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set LSR_TEMT [regs LSR_TEMT]
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# convert the 'char' to digit
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set tmp [ scan $char %c ]
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# /* wait for room in the tx FIFO on FFUART */
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while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
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mww $UART0_THR $tmp
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if { $char == "\n" } { putcUART0 \r }
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}
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proc putsUART0 {str} {
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set index 0
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set len [string length $str]
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while { $index < $len } {
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putcUART0 [string index $str $index]
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set index [expr $index + 1]
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}
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}
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proc trainDDR2 {} {
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set ARAM_BASEADDR [regs ARAM_BASEADDR]
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# you must have run 'reset init' or u-boot
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# load the training code to ARAM
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load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
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# set PC to start of NOR (at boot 0x20000000 = 0x0)
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reg pc $ARAM_BASEADDR
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# run
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resume
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}
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proc flashUBOOT {} {
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# this will update uboot on NOR partition
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
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# setup CS0 controller for NOR
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setupNOR
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# make sure we are accessing the lower part of NOR
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lowGPIO5
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flash probe 0
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puts "Erasing sectors 0-3 for uboot"
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flash erase_sector 0 0 3
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puts "Programming u-boot, takes about 4-5 min for 256kb"
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flash write_image ./images/u-boot.bin $EXP_CS0_BASEADDR
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} |