128 lines
4.6 KiB
ArmAsm
128 lines
4.6 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2019 by Andreas Bolsch *
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* andreas.bolsch@mni.thm.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m0
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.thumb
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.thumb_func
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/* Params:
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* r0 - total count (bytes), remaining bytes (out, 0 means successful)
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* r1 - flash page size
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* r2 - address offset into flash
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* r3 - QSPI io_base
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* r8 - fifo start
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* r9 - fifo end + 1
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* Clobbered:
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* r4 - wp
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* r5 - address of QSPI_DR
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* r7 - tmp
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*/
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#include "../../../../src/flash/nor/stmqspi.h"
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.macro qspi_abort
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movs r5, #(1<<SPI_ABORT) /* abort bit mask */
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ldr r7, [r3, #QSPI_CR] /* get QSPI_CR register */
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orrs r7, r7, r5 /* set abort bit */
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str r7, [r3, #QSPI_CR] /* store new CR register */
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.endm
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.macro wait_busy
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0:
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ldr r7, [r3, #QSPI_SR] /* load status */
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lsrs r7, r7, #(SPI_BUSY+1) /* shift BUSY into C */
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bcs 0b /* loop until BUSY cleared */
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movs r7, #(1<<SPI_TCF) /* TCF bitmask */
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str r7, [r3, #QSPI_FCR] /* clear TCF flag */
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.endm
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start:
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subs r0, r0, #1 /* decrement count for DLR */
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subs r1, r1, #1 /* page size mask and for DLR */
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ldr r4, wp /* load wp */
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start_read:
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qspi_abort /* start in clean state */
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movs r5, #QSPI_DR /* load QSPI_DR address offset */
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adds r5, r5, r3 /* address of QSPI_DR */
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wait_busy
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mov r7, r2 /* get current start address */
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orrs r7, r7, r1 /* end of current page */
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subs r7, r7, r2 /* count-1 to end of page */
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cmp r7, r0 /* if this count <= remaining */
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bls write_dlr /* then read to end of page */
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mov r7, r0 /* else read all remaining */
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write_dlr:
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str r7, [r3, #QSPI_DLR] /* size-1 in DLR register */
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ldr r7, ccr_page_read /* CCR for page read */
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str r7, [r3, #QSPI_CCR] /* initiate transfer */
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str r2, [r3, #QSPI_AR] /* store SPI start address */
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ldr r7, [r3, #QSPI_SR] /* wait for command startup */
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read_loop:
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ldrb r7, [r5] /* read next byte from DR */
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strb r7, [r4, #0] /* write next byte */
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adds r4, r4, #1 /* increment internal wp */
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cmp r4, r9 /* internal wp beyond end? */
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blo wait_fifo /* if no, then ok */
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mov r4, r8 /* else wrap around */
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wait_fifo:
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ldr r7, rp /* get rp */
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cmp r7, #0 /* if rp equals 0 */
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beq exit /* then abort */
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cmp r4, r7 /* check if fifo full */
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beq wait_fifo /* wait until not full */
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adr r7, wp /* get address of wp */
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str r4, [r7] /* store updated wp */
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adds r2, r2, #1 /* increment address */
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subs r0, r0, #1 /* decrement (count-1) */
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bmi exit /* stop if no data left */
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tst r2, r1 /* page end ? */
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bne read_loop /* if not, then next byte */
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page_end:
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bal start_read /* then next page */
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exit:
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adds r0, r0, #1 /* increment count due to the -1 */
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qspi_abort /* to idle state */
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.align 2 /* align to word, bkpt is 4 words */
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bkpt #0 /* before code end for exit_point */
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.align 2 /* align to word */
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.space 4 /* not used */
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.space 4 /* not used */
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.space 4 /* not used */
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.space 4 /* not used */
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.space 4 /* not used */
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.space 4 /* not used */
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.space 4 /* not used */
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.space 4 /* not used */
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.space 4 /* not used */
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ccr_page_read:
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.space 4 /* QSPI_CCR value for read command */
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.space 4 /* not used */
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.space 4 /* not used */
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.equ wp, . /* wp, uint32_t */
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.equ rp, wp + 4 /* rp, uint32_t */
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.equ buffer, rp + 4 /* buffer follows right away */
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