233 lines
6.3 KiB
ArmAsm
233 lines
6.3 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2014 by Mahavir Jain <mjain@marvell.com> *
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* *
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* Adapted from (contrib/loaders/flash/lpcspifi_write.S): *
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* Copyright (C) 2012 by George Harris *
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* george@luminairecoffee.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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/*
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* For compilation:
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* arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c contrib/loaders/flash/mrvlqspi_write.S
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* arm-none-eabi-objcopy -O binary mrvlqspi_write.o code.bin
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* Copy code.bin into mrvlqspi flash driver
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*/
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/*
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* Params :
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* r0 = workarea start, status (out)
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* r1 = workarea end
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* r2 = target address (offset from flash base)
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* r3 = count (bytes)
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* r4 = page size
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* r5 = qspi base address
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* Clobbered:
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* r7 - rp
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* r8 - wp, tmp
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* r9 - send/receive data
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* r10 - current page end address
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*/
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#define CNTL 0x0
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#define CONF 0x4
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#define DOUT 0x8
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#define DIN 0xc
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#define INSTR 0x10
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#define ADDR 0x14
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#define RDMODE 0x18
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#define HDRCNT 0x1c
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#define DINCNT 0x20
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#define SS_EN (1 << 0)
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#define XFER_RDY (1 << 1)
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#define RFIFO_EMPTY (1 << 4)
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#define WFIFO_EMPTY (1 << 6)
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#define WFIFO_FULL (1 << 7)
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#define FIFO_FLUSH (1 << 9)
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#define RW_EN (1 << 13)
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#define XFER_STOP (1 << 14)
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#define XFER_START (1 << 15)
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#define INS_WRITE_ENABLE 0x06
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#define INS_READ_STATUS 0x05
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#define INS_PAGE_PROGRAM 0x02
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init:
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mov.w r10, #0x00
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find_next_page_boundary:
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add r10, r4 /* Increment to the next page */
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cmp r10, r2
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/* If we have not reached the next page boundary after the target address, keep going */
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bls find_next_page_boundary
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write_enable:
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/* Flush read/write fifos */
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bl flush_fifo
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/* Instruction byte 1 */
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movs r8, #0x1
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str r8, [r5, #HDRCNT]
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/* Set write enable instruction */
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movs r8, #INS_WRITE_ENABLE
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str r8, [r5, #INSTR]
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movs r9, #0x1
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bl start_tx
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bl stop_tx
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page_program:
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/* Instruction byte 1, Addr byte 3 */
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movs r8, #0x31
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str r8, [r5, #HDRCNT]
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/* Todo: set addr and data pin to single */
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write_address:
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mov r8, r2
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str r8, [r5, #ADDR]
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/* Set page program instruction */
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movs r8, #INS_PAGE_PROGRAM
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str r8, [r5, #INSTR]
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/* Start write transfer */
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movs r9, #0x1
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bl start_tx
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wait_fifo:
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ldr r8, [r0] /* read the write pointer */
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cmp r8, #0 /* if it's zero, we're gonzo */
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beq exit
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ldr r7, [r0, #4] /* read the read pointer */
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cmp r7, r8 /* wait until they are not equal */
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beq wait_fifo
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write:
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ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
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bl write_data /* send the byte to the flash chip */
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cmp r7, r1 /* wrap the read pointer if it is at the end */
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it cs
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addcs r7, r0, #8 /* skip loader args */
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str r7, [r0, #4] /* store the new read pointer */
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subs r3, r3, #1 /* decrement count */
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cmp r3, #0 /* Exit if we have written everything */
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beq write_wait
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add r2, #1 /* Increment flash address by 1 */
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cmp r10, r2 /* See if we have reached the end of a page */
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bne wait_fifo /* If not, keep writing bytes */
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write_wait:
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bl stop_tx /* Otherwise, end the command and keep going w/ the next page */
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add r10, r4 /* Move up the end-of-page address by the page size*/
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check_flash_busy: /* Wait for the flash to finish the previous page write */
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/* Flush read/write fifos */
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bl flush_fifo
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/* Instruction byte 1 */
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movs r8, #0x1
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str r8, [r5, #HDRCNT]
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/* Continuous data in of status register */
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movs r8, #0x0
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str r8, [r5, #DINCNT]
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/* Set write enable instruction */
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movs r8, #INS_READ_STATUS
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str r8, [r5, #INSTR]
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/* Start read transfer */
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movs r9, #0x0
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bl start_tx
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wait_flash_busy:
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bl read_data
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and.w r9, r9, #0x1
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cmp r9, #0x0
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bne.n wait_flash_busy
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bl stop_tx
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cmp r3, #0
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bne.n write_enable /* If it is done, start a new page write */
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b exit /* All data written, exit */
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write_data: /* Send/receive 1 byte of data over QSPI */
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ldr r8, [r5, #CNTL]
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lsls r8, r8, #24
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bmi.n write_data
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str r9, [r5, #DOUT]
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bx lr
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read_data: /* Read 1 byte of data over QSPI */
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ldr r8, [r5, #CNTL]
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lsls r8, r8, #27
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bmi.n read_data
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ldr r9, [r5, #DIN]
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bx lr
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flush_fifo: /* Flush read write fifos */
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ldr r8, [r5, #CONF]
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orr.w r8, r8, #FIFO_FLUSH
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str r8, [r5, #CONF]
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flush_reset:
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ldr r8, [r5, #CONF]
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lsls r8, r8, #22
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bmi.n flush_reset
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bx lr
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start_tx:
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ldr r8, [r5, #CNTL]
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orr.w r8, r8, #SS_EN
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str r8, [r5, #CNTL]
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xfer_rdy:
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ldr r8, [r5, #CNTL]
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lsls r8, r8, #30
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bpl.n xfer_rdy
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ldr r8, [r5, #CONF]
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bfi r8, r9, #13, #1
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orr.w r8, r8, #XFER_START
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str r8, [r5, #CONF]
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bx lr
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stop_tx:
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ldr r8, [r5, #CNTL]
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lsls r8, r8, #30
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bpl.n stop_tx
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wfifo_wait:
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ldr r8, [r5, #CNTL]
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lsls r8, r8, #25
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bpl.n wfifo_wait
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ldr r8, [r5, #CONF]
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orr.w r8, r8, #XFER_STOP
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str r8, [r5, #CONF]
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xfer_start:
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ldr r8, [r5, #CONF]
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lsls r8, r8, #16
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bmi.n xfer_start
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ss_disable:
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# Disable SS_EN
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ldr r8, [r5, #CNTL]
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bic.w r8, r8, #SS_EN
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str r8, [r5, #CNTL]
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wait:
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ldr r8, [r5, #CNTL]
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lsls r8, r8, #30
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bpl.n wait
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bx lr
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error:
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movs r0, #0
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str r0, [r2, #4] /* set rp = 0 on error */
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exit:
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mov r0, r6
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bkpt #0x00
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.end
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