131 lines
3.7 KiB
INI
131 lines
3.7 KiB
INI
######################################
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# Target: DIGI ConnectCore Wi-9C
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######################################
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reset_config trst_and_srst
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# FIXME use some standard target config, maybe create one from this
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#
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# source [find target/...cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME ns9360
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# This config file was defaulting to big endian..
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set _ENDIAN big
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}
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# What's a good fallback frequency for this board if RCLK is
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# not available??
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jtag_rclk 1000
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x07926031
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}
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set _TARGETNAME $_CHIPNAME.cpu
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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adapter_nsrst_delay 200
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jtag_ntrst_delay 0
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######################
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# Target configuration
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######################
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -event reset-init {
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mww 0x90600104 0x33313333
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mww 0xA0700000 0x00000001 # Enable the memory controller.
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mww 0xA0700024 0x00000006 # Set the refresh counter 6
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mww 0xA0700028 0x00000001 #
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mww 0xA0700030 0x00000001 # Set the precharge period
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mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
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mww 0xA070003C 0x00000001 # tAPR
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mww 0xA0700040 0x00000005 # tDAL
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mww 0xA0700044 0x00000001 # tWR
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mww 0xA0700048 0x00000006 # tRC 32 clock cycles
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mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
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mww 0xA0700054 0x00000001 # tRRD
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mww 0xA0700058 0x00000001 # tMRD
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mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
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mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
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mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
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mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
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#
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mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
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#
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mww 0xA0700020 0x00000103 # issue SDRAM PALL command
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#
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mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
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#
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# Add some dummy writes to give the SDRAM time to settle, it needs two
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# AHB clock cycles, here we poke in the debugger flag, this lets
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# the software know that we are in the debugger
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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#
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
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#
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mww 0xA0700024 0x00000030 # Set the refresh counter to 30
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mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
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#
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# Next we perform a read of RAM.
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# mw = move word.
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mdw 0x00022000
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# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
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#
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mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
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mww 0xA0700100 0x00084280 # Enable buffer access
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mww 0xA0700120 0x00084280 # Enable buffer access
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mww 0xA0700140 0x00084280 # Enable buffer access
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mww 0xA0700160 0x00084280 # Enable buffer access
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#Set byte lane state (static mem 1)"
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mww 0xA0700220 0x00000082
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#Flash Start
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mww 0xA09001F8 0x50000000
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#Flash Mask Reg
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mww 0xA09001FC 0xFF000001
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mww 0xA0700028 0x00000001
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# RAMAddr = 0x00020000
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# RAMSize = 0x00004000
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# Set the processor mode
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reg cpsr 0xd3
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}
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$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
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#####################
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# Flash configuration
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#####################
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#M29DW323DB - not working
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#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME
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