341 lines
8.6 KiB
C
341 lines
8.6 KiB
C
/***************************************************************************
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* Copyright (C) 2015 by David Ung *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARMV8_H
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#define OPENOCD_TARGET_ARMV8_H
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#include "arm_adi_v5.h"
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#include "arm.h"
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#include "armv4_5_mmu.h"
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#include "armv4_5_cache.h"
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#include "armv8_dpm.h"
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#include "arm_cti.h"
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enum {
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ARMV8_R0 = 0,
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ARMV8_R1,
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ARMV8_R2,
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ARMV8_R3,
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ARMV8_R4,
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ARMV8_R5,
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ARMV8_R6,
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ARMV8_R7,
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ARMV8_R8,
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ARMV8_R9,
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ARMV8_R10,
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ARMV8_R11,
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ARMV8_R12,
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ARMV8_R13,
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ARMV8_R14,
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ARMV8_R15,
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ARMV8_R16,
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ARMV8_R17,
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ARMV8_R18,
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ARMV8_R19,
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ARMV8_R20,
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ARMV8_R21,
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ARMV8_R22,
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ARMV8_R23,
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ARMV8_R24,
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ARMV8_R25,
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ARMV8_R26,
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ARMV8_R27,
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ARMV8_R28,
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ARMV8_R29,
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ARMV8_R30,
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ARMV8_SP = 31,
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ARMV8_PC = 32,
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ARMV8_xPSR = 33,
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ARMV8_V0 = 34,
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ARMV8_V1,
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ARMV8_V2,
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ARMV8_V3,
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ARMV8_V4,
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ARMV8_V5,
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ARMV8_V6,
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ARMV8_V7,
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ARMV8_V8,
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ARMV8_V9,
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ARMV8_V10,
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ARMV8_V11,
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ARMV8_V12,
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ARMV8_V13,
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ARMV8_V14,
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ARMV8_V15,
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ARMV8_V16,
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ARMV8_V17,
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ARMV8_V18,
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ARMV8_V19,
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ARMV8_V20,
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ARMV8_V21,
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ARMV8_V22,
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ARMV8_V23,
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ARMV8_V24,
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ARMV8_V25,
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ARMV8_V26,
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ARMV8_V27,
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ARMV8_V28,
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ARMV8_V29,
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ARMV8_V30,
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ARMV8_V31,
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ARMV8_FPSR,
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ARMV8_FPCR,
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ARMV8_ELR_EL1 = 68,
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ARMV8_ESR_EL1 = 69,
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ARMV8_SPSR_EL1 = 70,
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ARMV8_ELR_EL2 = 71,
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ARMV8_ESR_EL2 = 72,
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ARMV8_SPSR_EL2 = 73,
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ARMV8_ELR_EL3 = 74,
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ARMV8_ESR_EL3 = 75,
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ARMV8_SPSR_EL3 = 76,
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ARMV8_LAST_REG,
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};
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enum run_control_op {
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ARMV8_RUNCONTROL_UNKNOWN = 0,
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ARMV8_RUNCONTROL_RESUME = 1,
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ARMV8_RUNCONTROL_HALT = 2,
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ARMV8_RUNCONTROL_STEP = 3,
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};
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#define ARMV8_COMMON_MAGIC 0x0A450AAA
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/* VA to PA translation operations opc2 values*/
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#define V2PCWPR 0
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#define V2PCWPW 1
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#define V2PCWUR 2
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#define V2PCWUW 3
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#define V2POWPR 4
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#define V2POWPW 5
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#define V2POWUR 6
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#define V2POWUW 7
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/* L210/L220 cache controller support */
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struct armv8_l2x_cache {
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uint32_t base;
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uint32_t way;
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};
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struct armv8_cachesize {
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uint32_t level_num;
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/* cache dimensionning */
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uint32_t linelen;
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uint32_t associativity;
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uint32_t nsets;
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uint32_t cachesize;
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/* info for set way operation on cache */
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uint32_t index;
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uint32_t index_shift;
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uint32_t way;
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uint32_t way_shift;
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};
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/* information about one architecture cache at any level */
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struct armv8_arch_cache {
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int ctype; /* cache type, CLIDR encoding */
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struct armv8_cachesize d_u_size; /* data cache */
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struct armv8_cachesize i_size; /* instruction cache */
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};
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struct armv8_cache_common {
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int info;
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int loc;
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uint32_t iminline;
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uint32_t dminline;
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struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
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int i_cache_enabled;
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int d_u_cache_enabled;
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/* l2 external unified cache if some */
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void *l2_cache;
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int (*flush_all_data_cache)(struct target *target);
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int (*display_cache_info)(struct command_context *cmd_ctx,
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struct armv8_cache_common *armv8_cache);
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};
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struct armv8_mmu_common {
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/* following field mmu working way */
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int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
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uint64_t ttbr0_mask;/* masked to be used */
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uint32_t ttbcr; /* cache for ttbcr register */
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uint32_t ttbr_mask[2];
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uint32_t ttbr_range[2];
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int (*read_physical_memory)(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer);
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struct armv8_cache_common armv8_cache;
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uint32_t mmu_enabled;
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};
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struct armv8_common {
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struct arm arm;
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int common_magic;
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struct reg_cache *core_cache;
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/* Core Debug Unit */
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struct arm_dpm dpm;
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uint32_t debug_base;
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struct adiv5_ap *debug_ap;
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const uint32_t *opcodes;
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/* mdir */
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uint8_t multi_processor_system;
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uint8_t cluster_id;
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uint8_t cpu_id;
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/* armv8 aarch64 need below information for page translation */
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uint8_t va_size;
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uint8_t pa_size;
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uint32_t page_size;
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uint64_t ttbr_base;
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struct armv8_mmu_common armv8_mmu;
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struct arm_cti *cti;
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/* last run-control command issued to this target (resume, halt, step) */
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enum run_control_op last_run_control_op;
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/* Direct processor core register read and writes */
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int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
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int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
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/* SIMD/FPU registers read/write interface */
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int (*read_reg_u128)(struct armv8_common *armv8, int num,
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uint64_t *lvalue, uint64_t *hvalue);
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int (*write_reg_u128)(struct armv8_common *armv8, int num,
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uint64_t lvalue, uint64_t hvalue);
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int (*examine_debug_reason)(struct target *target);
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int (*post_debug_entry)(struct target *target);
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void (*pre_restore_context)(struct target *target);
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};
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static inline struct armv8_common *
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target_to_armv8(struct target *target)
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{
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return container_of(target->arch_info, struct armv8_common, arm);
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}
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static inline bool is_armv8(struct armv8_common *armv8)
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{
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return armv8->common_magic == ARMV8_COMMON_MAGIC;
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}
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/* register offsets from armv8.debug_base */
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#define CPUV8_DBG_MAINID0 0xD00
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#define CPUV8_DBG_CPUFEATURE0 0xD20
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#define CPUV8_DBG_DBGFEATURE0 0xD28
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#define CPUV8_DBG_MEMFEATURE0 0xD38
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#define CPUV8_DBG_LOCKACCESS 0xFB0
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#define CPUV8_DBG_LOCKSTATUS 0xFB4
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#define CPUV8_DBG_EDESR 0x20
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#define CPUV8_DBG_EDECR 0x24
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#define CPUV8_DBG_WFAR0 0x30
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#define CPUV8_DBG_WFAR1 0x34
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#define CPUV8_DBG_DSCR 0x088
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#define CPUV8_DBG_DRCR 0x090
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#define CPUV8_DBG_ECCR 0x098
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#define CPUV8_DBG_PRCR 0x310
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#define CPUV8_DBG_PRSR 0x314
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#define CPUV8_DBG_DTRRX 0x080
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#define CPUV8_DBG_ITR 0x084
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#define CPUV8_DBG_SCR 0x088
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#define CPUV8_DBG_DTRTX 0x08c
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#define CPUV8_DBG_BVR_BASE 0x400
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#define CPUV8_DBG_BCR_BASE 0x408
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#define CPUV8_DBG_WVR_BASE 0x800
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#define CPUV8_DBG_WCR_BASE 0x808
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#define CPUV8_DBG_VCR 0x01C
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#define CPUV8_DBG_OSLAR 0x300
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#define CPUV8_DBG_AUTHSTATUS 0xFB8
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#define PAGE_SIZE_4KB 0x1000
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#define PAGE_SIZE_4KB_LEVEL0_BITS 39
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#define PAGE_SIZE_4KB_LEVEL1_BITS 30
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#define PAGE_SIZE_4KB_LEVEL2_BITS 21
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#define PAGE_SIZE_4KB_LEVEL3_BITS 12
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#define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
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#define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
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#define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
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#define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
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#define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
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int armv8_arch_state(struct target *target);
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int armv8_read_mpidr(struct armv8_common *armv8);
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int armv8_identify_cache(struct armv8_common *armv8);
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int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
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int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
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target_addr_t *val, int meminfo);
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int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
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int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
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struct armv8_cache_common *armv8_cache);
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void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
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static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
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{
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switch (core_mode) {
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/* Aarch32 modes */
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case ARM_MODE_USR:
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return 0;
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case ARM_MODE_SVC:
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case ARM_MODE_ABT: /* FIXME: EL3? */
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case ARM_MODE_IRQ: /* FIXME: EL3? */
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case ARM_MODE_FIQ: /* FIXME: EL3? */
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case ARM_MODE_UND: /* FIXME: EL3? */
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case ARM_MODE_SYS: /* FIXME: EL3? */
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return 1;
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/* case ARM_MODE_HYP:
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* return 2;
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*/
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case ARM_MODE_MON:
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return 3;
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/* all Aarch64 modes */
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default:
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return (core_mode >> 2) & 3;
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}
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}
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void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
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int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
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extern void armv8_free_reg_cache(struct target *target);
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extern const struct command_registration armv8_command_handlers[];
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#endif /* OPENOCD_TARGET_ARMV8_H */
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