ff6d0704ec
Add support for Xilinx Virtual Cable over PCIe JTAG controller. It is commonly used in Xilinx based PCI Express designs with JTAG IP in the FPGA fabric. Access to the JTAG registers happens via the PCI Express extended configuration space. This can be used to debug soft-cores instantiated in the FPGA fabric. The clang static checker doesn't find any new problems with this change. Change-Id: Ib12ede0d1f26dacfda808d5e05b947b640c5bde7 Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: http://openocd.zylin.com/5314 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Marex Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> |
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manual | ||
Makefile.am | ||
fdl.texi | ||
openocd.1 | ||
openocd.texi |