155 lines
4.0 KiB
INI
155 lines
4.0 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
|
||
#
|
||
# The ESP32-S3 only supports JTAG.
|
||
transport select jtag
|
||
|
||
set CPU_MAX_ADDRESS 0xFFFFFFFF
|
||
source [find bitsbytes.tcl]
|
||
source [find memory.tcl]
|
||
source [find mmr_helpers.tcl]
|
||
# Source the ESP common configuration file
|
||
source [find target/esp_common.cfg]
|
||
|
||
|
||
if { [info exists CHIPNAME] } {
|
||
set _CHIPNAME $CHIPNAME
|
||
} else {
|
||
set _CHIPNAME esp32s3
|
||
}
|
||
|
||
if { [info exists CPUTAPID] } {
|
||
set _CPUTAPID $CPUTAPID
|
||
} else {
|
||
set _CPUTAPID 0x120034e5
|
||
}
|
||
|
||
if { [info exists ESP32_S3_ONLYCPU] } {
|
||
set _ONLYCPU $ESP32_S3_ONLYCPU
|
||
} else {
|
||
set _ONLYCPU 2
|
||
}
|
||
|
||
set _CPU0NAME cpu0
|
||
set _CPU1NAME cpu1
|
||
set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
|
||
set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
|
||
|
||
jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
|
||
if { $_ONLYCPU != 1 } {
|
||
jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
|
||
} else {
|
||
jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
|
||
}
|
||
|
||
proc esp32s3_memprot_is_enabled { } {
|
||
# SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
|
||
if { [get_mmr_bit 0x600C10C0 0] != 0 } {
|
||
return 1
|
||
}
|
||
# SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
|
||
if { [get_mmr_bit 0x600C1124 0] != 0 } {
|
||
return 1
|
||
}
|
||
# SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
|
||
if { [get_mmr_bit 0x600C11D0 0] != 0 } {
|
||
return 1
|
||
}
|
||
# IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
|
||
if { [get_mmr_bit 0x600C10D8 0] != 0 } {
|
||
return 1
|
||
}
|
||
# DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
|
||
if { [get_mmr_bit 0x600C10FC 0] != 0 } {
|
||
return 1
|
||
}
|
||
# SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
|
||
if { [get_mmr_bit 0x600C10E4 0] != 0 } {
|
||
return 1
|
||
}
|
||
# SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
|
||
if { [get_mmr_bit 0x600C10F0 0] != 0 } {
|
||
return 1
|
||
}
|
||
# SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
|
||
if { [get_mmr_bit 0x600C1104 0] != 0 } {
|
||
return 1
|
||
}
|
||
# SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
|
||
if { [get_mmr_bit 0x600C1114 0] != 0 } {
|
||
return 1
|
||
}
|
||
# SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
|
||
if { [get_mmr_bit 0x600C119C 0] != 0 } {
|
||
return 1
|
||
}
|
||
# SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
|
||
if { [get_mmr_bit 0x600C1248 0] != 0 } {
|
||
return 1
|
||
}
|
||
return 0
|
||
}
|
||
|
||
# PRO-CPU
|
||
target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
|
||
# APP-CPU
|
||
if { $_ONLYCPU != 1 } {
|
||
target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
|
||
target smp $_TARGETNAME_0 $_TARGETNAME_1
|
||
}
|
||
|
||
$_TARGETNAME_0 xtensa maskisr on
|
||
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
|
||
$_TARGETNAME_0 configure -event examine-end {
|
||
# Need to enable to set 'semihosting_basedir'
|
||
arm semihosting enable
|
||
arm semihosting_resexit enable
|
||
if { [info exists _SEMIHOST_BASEDIR] } {
|
||
if { $_SEMIHOST_BASEDIR != "" } {
|
||
arm semihosting_basedir $_SEMIHOST_BASEDIR
|
||
}
|
||
}
|
||
}
|
||
|
||
if { $_ONLYCPU != 1 } {
|
||
$_TARGETNAME_1 configure -event examine-end {
|
||
# Need to enable to set 'semihosting_basedir'
|
||
arm semihosting enable
|
||
arm semihosting_resexit enable
|
||
if { [info exists _SEMIHOST_BASEDIR] } {
|
||
if { $_SEMIHOST_BASEDIR != "" } {
|
||
arm semihosting_basedir $_SEMIHOST_BASEDIR
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
$_TARGETNAME_0 configure -event gdb-attach {
|
||
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
|
||
# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
|
||
halt 1000
|
||
if { [esp32s3_memprot_is_enabled] } {
|
||
# 'reset halt' to disable memory protection and allow flasher to work correctly
|
||
echo "Memory protection is enabled. Reset target to disable it..."
|
||
reset halt
|
||
}
|
||
}
|
||
$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
|
||
|
||
if { $_ONLYCPU != 1 } {
|
||
$_TARGETNAME_1 configure -event gdb-attach {
|
||
$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
|
||
# necessary to auto-probe flash bank when GDB is connected
|
||
halt 1000
|
||
if { [esp32s3_memprot_is_enabled] } {
|
||
# 'reset halt' to disable memory protection and allow flasher to work correctly
|
||
echo "Memory protection is enabled. Reset target to disable it..."
|
||
reset halt
|
||
}
|
||
}
|
||
$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
|
||
}
|
||
|
||
gdb_breakpoint_override hard
|
||
|
||
source [find target/xtensa-core-esp32s3.cfg]
|