379 lines
10 KiB
C
379 lines
10 KiB
C
/***************************************************************************
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* Copyright (C) 2015 by Oleksij Rempel *
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* linux@rempel-privat.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "jtag/interface.h"
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#include "arm.h"
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#include "armv7a.h"
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#include "armv7a_cache.h"
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#include <helper/time_support.h>
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#include "target.h"
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#include "target_type.h"
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static int arm7a_l2x_sanity_check(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
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(armv7a->armv7a_mmu.armv7a_cache.outer_cache);
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("%s: target not halted", __func__);
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return ERROR_TARGET_NOT_HALTED;
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}
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if (!l2x_cache || !l2x_cache->base) {
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LOG_DEBUG("l2x is not configured!");
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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/*
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* clean and invalidate complete l2x cache
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*/
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int arm7a_l2x_flush_all_data(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
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(armv7a->armv7a_mmu.armv7a_cache.outer_cache);
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uint32_t l2_way_val;
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int retval;
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retval = arm7a_l2x_sanity_check(target);
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if (retval)
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return retval;
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l2_way_val = (1 << l2x_cache->way) - 1;
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return target_write_phys_u32(target,
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l2x_cache->base + L2X0_CLEAN_INV_WAY,
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l2_way_val);
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}
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int armv7a_l2x_cache_flush_virt(struct target *target, target_addr_t virt,
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uint32_t size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
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(armv7a->armv7a_mmu.armv7a_cache.outer_cache);
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/* FIXME: different controllers have different linelen? */
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uint32_t i, linelen = 32;
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int retval;
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retval = arm7a_l2x_sanity_check(target);
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if (retval)
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return retval;
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for (i = 0; i < size; i += linelen) {
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target_addr_t pa, offs = virt + i;
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/* FIXME: use less verbose virt2phys? */
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retval = target->type->virt2phys(target, offs, &pa);
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if (retval != ERROR_OK)
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goto done;
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retval = target_write_phys_u32(target,
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l2x_cache->base + L2X0_CLEAN_INV_LINE_PA, pa);
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if (retval != ERROR_OK)
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goto done;
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}
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return retval;
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done:
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LOG_ERROR("d-cache invalidate failed");
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return retval;
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}
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static int armv7a_l2x_cache_inval_virt(struct target *target, target_addr_t virt,
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uint32_t size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
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(armv7a->armv7a_mmu.armv7a_cache.outer_cache);
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/* FIXME: different controllers have different linelen */
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uint32_t i, linelen = 32;
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int retval;
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retval = arm7a_l2x_sanity_check(target);
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if (retval)
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return retval;
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for (i = 0; i < size; i += linelen) {
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target_addr_t pa, offs = virt + i;
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/* FIXME: use less verbose virt2phys? */
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retval = target->type->virt2phys(target, offs, &pa);
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if (retval != ERROR_OK)
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goto done;
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retval = target_write_phys_u32(target,
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l2x_cache->base + L2X0_INV_LINE_PA, pa);
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if (retval != ERROR_OK)
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goto done;
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}
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return retval;
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done:
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LOG_ERROR("d-cache invalidate failed");
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return retval;
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}
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static int armv7a_l2x_cache_clean_virt(struct target *target, target_addr_t virt,
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unsigned int size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
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(armv7a->armv7a_mmu.armv7a_cache.outer_cache);
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/* FIXME: different controllers have different linelen */
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uint32_t i, linelen = 32;
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int retval;
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retval = arm7a_l2x_sanity_check(target);
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if (retval)
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return retval;
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for (i = 0; i < size; i += linelen) {
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target_addr_t pa, offs = virt + i;
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/* FIXME: use less verbose virt2phys? */
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retval = target->type->virt2phys(target, offs, &pa);
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if (retval != ERROR_OK)
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goto done;
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retval = target_write_phys_u32(target,
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l2x_cache->base + L2X0_CLEAN_LINE_PA, pa);
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if (retval != ERROR_OK)
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goto done;
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}
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return retval;
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done:
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LOG_ERROR("d-cache invalidate failed");
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return retval;
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}
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static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
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struct armv7a_cache_common *armv7a_cache)
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{
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struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
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(armv7a_cache->outer_cache);
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if (armv7a_cache->info == -1) {
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command_print(cmd_ctx, "cache not yet identified");
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return ERROR_OK;
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}
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command_print(cmd_ctx,
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"L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
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l2x_cache->base, l2x_cache->way);
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return ERROR_OK;
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}
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static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
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{
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struct armv7a_l2x_cache *l2x_cache;
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struct target_list *head = target->head;
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struct target *curr;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
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LOG_ERROR("L2 cache was already initialised\n");
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return ERROR_FAIL;
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}
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l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
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l2x_cache->base = base;
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l2x_cache->way = way;
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armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
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/* initialize all targets in this cluster (smp target)
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* l2 cache must be configured after smp declaration */
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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if (curr != target) {
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armv7a = target_to_armv7a(curr);
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if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
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LOG_ERROR("smp target : cache l2 already initialized\n");
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return ERROR_FAIL;
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}
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armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
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}
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head = head->next;
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}
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return ERROR_OK;
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}
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COMMAND_HANDLER(arm7a_l2x_cache_info_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct armv7a_common *armv7a = target_to_armv7a(target);
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int retval;
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retval = arm7a_l2x_sanity_check(target);
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if (retval)
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return retval;
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return arm7a_handle_l2x_cache_info_command(CMD_CTX,
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&armv7a->armv7a_mmu.armv7a_cache);
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}
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COMMAND_HANDLER(arm7a_l2x_cache_flush_all_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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return arm7a_l2x_flush_all_data(target);
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}
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COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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target_addr_t virt;
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uint32_t size;
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
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return armv7a_l2x_cache_flush_virt(target, virt, size);
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}
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COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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target_addr_t virt;
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uint32_t size;
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
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return armv7a_l2x_cache_inval_virt(target, virt, size);
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}
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COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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target_addr_t virt;
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uint32_t size;
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
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return armv7a_l2x_cache_clean_virt(target, virt, size);
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}
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/* FIXME: should we configure way size? or controller type? */
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COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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uint32_t base, way;
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if (CMD_ARGC != 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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/* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
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/* AP address is in bits 31:24 of DP_SELECT */
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return armv7a_l2x_cache_init(target, base, way);
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}
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static const struct command_registration arm7a_l2x_cache_commands[] = {
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{
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.name = "conf",
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.handler = armv7a_l2x_cache_conf_cmd,
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.mode = COMMAND_ANY,
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.help = "configure l2x cache ",
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.usage = "<base_addr> <number_of_way>",
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},
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{
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.name = "info",
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.handler = arm7a_l2x_cache_info_command,
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.mode = COMMAND_ANY,
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.help = "print cache realted information",
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.usage = "",
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},
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{
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.name = "flush_all",
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.handler = arm7a_l2x_cache_flush_all_command,
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.mode = COMMAND_ANY,
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.help = "flush complete l2x cache",
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.usage = "",
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},
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{
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.name = "flush",
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.handler = arm7a_l2x_cache_flush_virt_cmd,
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.mode = COMMAND_ANY,
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.help = "flush (clean and invalidate) l2x cache by virtual address offset and range size",
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.usage = "<virt_addr> [size]",
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},
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{
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.name = "inval",
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.handler = arm7a_l2x_cache_inval_virt_cmd,
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.mode = COMMAND_ANY,
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.help = "invalidate l2x cache by virtual address offset and range size",
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.usage = "<virt_addr> [size]",
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},
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{
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.name = "clean",
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.handler = arm7a_l2x_cache_clean_virt_cmd,
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.mode = COMMAND_ANY,
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.help = "clean l2x cache by virtual address address offset and range size",
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.usage = "<virt_addr> [size]",
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},
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COMMAND_REGISTRATION_DONE
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};
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const struct command_registration arm7a_l2x_cache_command_handler[] = {
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{
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.name = "l2x",
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.mode = COMMAND_ANY,
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.help = "l2x cache command group",
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.usage = "",
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.chain = arm7a_l2x_cache_commands,
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},
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COMMAND_REGISTRATION_DONE
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};
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