103 lines
2.7 KiB
INI
103 lines
2.7 KiB
INI
# script for stm32h7x family
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#
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# stm32h7 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32h7x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} {
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set _CPUTAPID 0x6ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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swj_newdap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
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# Clock after reset is HSI at 64 MHz, no need of PLL
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adapter_khz 1800
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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# use hardware reset, connect under reset
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reset_config srst_only srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# Enable D3 and D1 DBG clocks
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# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
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mmw 0x5C001004 0x00600000 0
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
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mmw 0x5C001004 0x00000187 0
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# Stop watchdog counters during halt
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# DBGMCU_APB3FZ1 |= WWDG1
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mmw 0x5C001034 0x00000040 0
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# DBGMCU_APB4FZ1 |= WDGLSD1
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mmw 0x5C001054 0x00040000 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0x5C001004 0x00100000 0
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}
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$_TARGETNAME configure -event reset-init {
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# Clock after reset is HSI at 64 MHz, no need of PLL
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adapter_khz 4000
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}
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# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
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# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
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# makes the data access cacheable. This allows reading and writing data in the
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# CPU cache from the debugger, which is far more useful than going straight to
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# RAM when operating on typical variables, and is generally no worse when
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# operating on special memory locations.
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$_CHIPNAME.dap apcsw 0x08000000 0x08000000
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