109 lines
3.6 KiB
ArmAsm
109 lines
3.6 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2017 by STMicroelectronics *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc. *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m7
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.thumb
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/*
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* Code limitations:
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* The workarea must have size multiple of 4 bytes, since R/W
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* operations are all at 32 bits.
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* The workarea must be big enough to contain 32 bytes of data,
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* thus the minimum size is (rp, wp, data) = 4 + 4 + 32 = 40 bytes.
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* To benefit from concurrent host write-to-buffer and target
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* write-to-flash, the workarea must be way bigger than the minimum.
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*/
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/*
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* Params :
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* r0 = workarea start, status (out)
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* r1 = workarea end
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* r2 = target address
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* r3 = count (256 bit words)
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* r4 = flash reg base
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*
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* Clobbered:
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* r5 - rp
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* r6 - wp, status, tmp
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* r7 - loop index, tmp
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*/
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#define STM32_FLASH_CR_OFFSET 0x0C /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
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#define STM32_CR_PROG 0x00000032 /* PSIZE64 | PG */
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#define STM32_SR_BUSY_MASK 0x00000001 /* BSY */
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#define STM32_SR_ERROR_MASK 0x03ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
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| INCERR | STRBERR | PGSERR | WRPERR */
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.thumb_func
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.global _start
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_start:
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ldr r5, [r0, #4] /* read rp */
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wait_fifo:
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ldr r6, [r0, #0] /* read wp */
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cbz r6, exit /* abort if wp == 0, status = 0 */
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subs r6, r6, r5 /* number of bytes available for read in r6 */
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ittt mi /* if wrapped around */
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addmi r6, r1 /* add size of buffer */
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submi r6, r0
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submi r6, #8
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cmp r6, #32 /* wait until 32 bytes are available */
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bcc wait_fifo
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mov r6, #STM32_CR_PROG
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str r6, [r4, #STM32_FLASH_CR_OFFSET]
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mov r7, #8 /* program by 8 words = 32 bytes */
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write_flash:
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ldr r6, [r5], #0x04 /* read one word from src, increment ptr */
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str r6, [r2], #0x04 /* write one word to dst, increment ptr */
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dsb
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cmp r5, r1 /* if rp >= end of buffer ... */
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it cs
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addcs r5, r0, #8 /* ... then wrap at buffer start */
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subs r7, r7, #1 /* decrement loop index */
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bne write_flash /* loop if not done */
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busy:
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ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
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tst r6, #STM32_SR_BUSY_MASK
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bne busy /* operation in progress, wait ... */
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ldr r7, =STM32_SR_ERROR_MASK
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tst r6, r7
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bne error /* fail... */
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str r5, [r0, #4] /* store rp */
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subs r3, r3, #1 /* decrement count */
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bne wait_fifo /* loop if not done */
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b exit
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error:
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movs r7, #0
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str r7, [r0, #4] /* set rp = 0 on error */
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exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0x00
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.pool
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