708 lines
19 KiB
C
708 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Copyright (C) 2009 by Alexei Babich *
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* Rezonans plc., Chelyabinsk, Russia *
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* impatt@mail.ru *
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***************************************************************************/
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/*
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* Freescale iMX3* OpenOCD NAND Flash controller support.
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*
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* Many thanks to Ben Dooks for writing s3c24xx driver.
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*/
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/*
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driver tested with STMicro NAND512W3A @imx31
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tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
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get_next_halfword_from_sram_buffer() not tested
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include "mx3.h"
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#include <target/target.h>
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static const char target_not_halted_err_msg[] =
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"target must be halted to use mx3 NAND flash controller";
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static const char data_block_size_err_msg[] =
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"minimal granularity is one half-word, %" PRIu32 " is incorrect";
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static const char sram_buffer_bounds_err_msg[] =
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"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
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static const char get_status_register_err_msg[] = "can't get NAND status";
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static uint32_t in_sram_address;
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static unsigned char sign_of_sequental_byte_read;
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static int test_iomux_settings(struct target *target, uint32_t value,
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uint32_t mask, const char *text);
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static int initialize_nf_controller(struct nand_device *nand);
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static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value);
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static int get_next_halfword_from_sram_buffer(struct target *target,
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uint16_t *value);
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static int poll_for_complete_op(struct target *target, const char *text);
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static int validate_target_state(struct nand_device *nand);
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static int do_data_output(struct nand_device *nand);
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static int imx31_command(struct nand_device *nand, uint8_t command);
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static int imx31_address(struct nand_device *nand, uint8_t address);
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NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
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{
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struct mx3_nf_controller *mx3_nf_info;
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mx3_nf_info = malloc(sizeof(struct mx3_nf_controller));
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if (!mx3_nf_info) {
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LOG_ERROR("no memory for nand controller");
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return ERROR_FAIL;
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}
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nand->controller_priv = mx3_nf_info;
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if (CMD_ARGC < 3)
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return ERROR_COMMAND_SYNTAX_ERROR;
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/*
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* check hwecc requirements
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*/
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{
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int hwecc_needed;
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hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
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if (hwecc_needed == 0)
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mx3_nf_info->flags.hw_ecc_enabled = 1;
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else
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mx3_nf_info->flags.hw_ecc_enabled = 0;
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}
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mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
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mx3_nf_info->fin = MX3_NF_FIN_NONE;
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mx3_nf_info->flags.target_little_endian =
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(nand->target->endianness == TARGET_LITTLE_ENDIAN);
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return ERROR_OK;
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}
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static int imx31_init(struct nand_device *nand)
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{
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struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
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struct target *target = nand->target;
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{
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/*
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* validate target state
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*/
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int validate_target_result;
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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}
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{
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uint16_t buffsize_register_content;
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target_read_u16(target, MX3_NF_BUFSIZ, &buffsize_register_content);
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mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
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}
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{
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uint32_t pcsr_register_content;
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target_read_u32(target, MX3_PCSR, &pcsr_register_content);
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if (!nand->bus_width) {
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nand->bus_width = (pcsr_register_content & 0x80000000) ? 16 : 8;
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} else {
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pcsr_register_content |= ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
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target_write_u32(target, MX3_PCSR, pcsr_register_content);
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}
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if (!nand->page_size) {
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nand->page_size = (pcsr_register_content & 0x40000000) ? 2048 : 512;
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} else {
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pcsr_register_content |= ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
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target_write_u32(target, MX3_PCSR, pcsr_register_content);
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}
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if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
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LOG_ERROR("NAND controller have only 1 kb SRAM, "
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"so pagesize 2048 is incompatible with it");
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}
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}
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{
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uint32_t cgr_register_content;
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target_read_u32(target, MX3_CCM_CGR2, &cgr_register_content);
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if (!(cgr_register_content & 0x00000300)) {
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LOG_ERROR("clock gating to EMI disabled");
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return ERROR_FAIL;
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}
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}
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{
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uint32_t gpr_register_content;
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target_read_u32(target, MX3_GPR, &gpr_register_content);
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if (gpr_register_content & 0x00000060) {
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LOG_ERROR("pins mode overridden by GPR");
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return ERROR_FAIL;
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}
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}
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{
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/*
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* testing IOMUX settings; must be in "functional-mode output and
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* functional-mode input" mode
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*/
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int test_iomux;
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test_iomux = ERROR_OK;
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test_iomux |= test_iomux_settings(target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
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test_iomux |= test_iomux_settings(target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
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test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x0000007f, "d7");
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if (nand->bus_width == 16) {
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test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x7f7f7f00, "d8,d9,d10");
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test_iomux |= test_iomux_settings(target, 0x43fac0cc, 0x7f7f7f7f, "d11,d12,d13,d14");
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test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x0000007f, "d15");
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}
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test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x7f7f7f00, "nfwp,nfce,nfrb");
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test_iomux |= test_iomux_settings(target, 0x43fac0d4, 0x7f7f7f7f,
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"nfwe,nfre,nfale,nfcle");
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if (test_iomux != ERROR_OK)
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return ERROR_FAIL;
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}
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initialize_nf_controller(nand);
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{
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int retval;
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uint16_t nand_status_content;
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retval = ERROR_OK;
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retval |= imx31_command(nand, NAND_CMD_STATUS);
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retval |= imx31_address(nand, 0x00);
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retval |= do_data_output(nand);
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if (retval != ERROR_OK) {
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LOG_ERROR(get_status_register_err_msg);
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return ERROR_FAIL;
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}
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target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
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if (!(nand_status_content & 0x0080)) {
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/*
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* is host-big-endian correctly ??
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*/
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LOG_INFO("NAND read-only");
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mx3_nf_info->flags.nand_readonly = 1;
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} else
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mx3_nf_info->flags.nand_readonly = 0;
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}
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return ERROR_OK;
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}
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static int imx31_read_data(struct nand_device *nand, void *data)
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{
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struct target *target = nand->target;
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{
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/*
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* validate target state
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*/
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int validate_target_result;
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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}
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{
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/*
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* get data from nand chip
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*/
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int try_data_output_from_nand_chip;
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try_data_output_from_nand_chip = do_data_output(nand);
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if (try_data_output_from_nand_chip != ERROR_OK)
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return try_data_output_from_nand_chip;
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}
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if (nand->bus_width == 16)
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get_next_halfword_from_sram_buffer(target, data);
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else
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get_next_byte_from_sram_buffer(target, data);
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return ERROR_OK;
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}
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static int imx31_write_data(struct nand_device *nand, uint16_t data)
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{
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LOG_ERROR("write_data() not implemented");
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return ERROR_NAND_OPERATION_FAILED;
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}
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static int imx31_reset(struct nand_device *nand)
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{
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/*
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* validate target state
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*/
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int validate_target_result;
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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initialize_nf_controller(nand);
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return ERROR_OK;
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}
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static int imx31_command(struct nand_device *nand, uint8_t command)
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{
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struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
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struct target *target = nand->target;
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{
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/*
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* validate target state
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*/
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int validate_target_result;
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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}
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switch (command) {
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case NAND_CMD_READOOB:
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command = NAND_CMD_READ0;
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in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
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* data_read() and
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* read_block_data() to
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* spare area in SRAM
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* buffer */
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break;
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case NAND_CMD_READ1:
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command = NAND_CMD_READ0;
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/*
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* offset == one half of page size
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*/
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in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
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break;
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default:
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in_sram_address = MX3_NF_MAIN_BUFFER0;
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}
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target_write_u16(target, MX3_NF_FCMD, command);
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/*
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* start command input operation (set MX3_NF_BIT_OP_DONE==0)
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*/
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target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
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{
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int poll_result;
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poll_result = poll_for_complete_op(target, "command");
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if (poll_result != ERROR_OK)
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return poll_result;
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}
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/*
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* reset cursor to begin of the buffer
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*/
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sign_of_sequental_byte_read = 0;
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switch (command) {
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case NAND_CMD_READID:
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mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
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mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
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break;
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case NAND_CMD_STATUS:
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mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
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mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
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break;
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case NAND_CMD_READ0:
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mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
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mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
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break;
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default:
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mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
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}
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return ERROR_OK;
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}
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static int imx31_address(struct nand_device *nand, uint8_t address)
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{
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struct target *target = nand->target;
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{
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/*
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* validate target state
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*/
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int validate_target_result;
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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}
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target_write_u16(target, MX3_NF_FADDR, address);
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/*
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* start address input operation (set MX3_NF_BIT_OP_DONE==0)
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*/
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target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
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{
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int poll_result;
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poll_result = poll_for_complete_op(target, "address");
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if (poll_result != ERROR_OK)
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return poll_result;
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}
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return ERROR_OK;
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}
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static int imx31_nand_ready(struct nand_device *nand, int tout)
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{
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uint16_t poll_complete_status;
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struct target *target = nand->target;
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{
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/*
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* validate target state
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*/
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int validate_target_result;
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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}
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do {
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target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
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if (poll_complete_status & MX3_NF_BIT_OP_DONE)
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return tout;
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alive_sleep(1);
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} while (tout-- > 0);
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return tout;
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}
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static int imx31_write_page(struct nand_device *nand, uint32_t page,
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uint8_t *data, uint32_t data_size, uint8_t *oob,
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uint32_t oob_size)
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{
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struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
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struct target *target = nand->target;
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if (data_size % 2) {
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LOG_ERROR(data_block_size_err_msg, data_size);
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (oob_size % 2) {
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LOG_ERROR(data_block_size_err_msg, oob_size);
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (!data) {
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LOG_ERROR("nothing to program");
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return ERROR_NAND_OPERATION_FAILED;
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}
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{
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/*
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* validate target state
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*/
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int retval;
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retval = validate_target_state(nand);
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if (retval != ERROR_OK)
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return retval;
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}
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{
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int retval = ERROR_OK;
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retval |= imx31_command(nand, NAND_CMD_SEQIN);
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retval |= imx31_address(nand, 0x00);
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retval |= imx31_address(nand, page & 0xff);
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retval |= imx31_address(nand, (page >> 8) & 0xff);
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if (nand->address_cycles >= 4) {
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retval |= imx31_address(nand, (page >> 16) & 0xff);
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if (nand->address_cycles >= 5)
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retval |= imx31_address(nand, (page >> 24) & 0xff);
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}
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target_write_buffer(target, MX3_NF_MAIN_BUFFER0, data_size, data);
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if (oob) {
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if (mx3_nf_info->flags.hw_ecc_enabled) {
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/*
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* part of spare block will be overridden by hardware
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* ECC generator
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*/
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LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
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}
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target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
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}
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/*
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* start data input operation (set MX3_NF_BIT_OP_DONE==0)
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*/
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target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
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{
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int poll_result;
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poll_result = poll_for_complete_op(target, "data input");
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if (poll_result != ERROR_OK)
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return poll_result;
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}
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retval |= imx31_command(nand, NAND_CMD_PAGEPROG);
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if (retval != ERROR_OK)
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return retval;
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/*
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* check status register
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*/
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{
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uint16_t nand_status_content;
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retval = ERROR_OK;
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retval |= imx31_command(nand, NAND_CMD_STATUS);
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retval |= imx31_address(nand, 0x00);
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retval |= do_data_output(nand);
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if (retval != ERROR_OK) {
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LOG_ERROR(get_status_register_err_msg);
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return retval;
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}
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target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
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if (nand_status_content & 0x0001) {
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/*
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* is host-big-endian correctly ??
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*/
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return ERROR_NAND_OPERATION_FAILED;
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}
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}
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}
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return ERROR_OK;
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}
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static int imx31_read_page(struct nand_device *nand, uint32_t page,
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uint8_t *data, uint32_t data_size, uint8_t *oob,
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uint32_t oob_size)
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{
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struct target *target = nand->target;
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if (data_size % 2) {
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LOG_ERROR(data_block_size_err_msg, data_size);
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (oob_size % 2) {
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LOG_ERROR(data_block_size_err_msg, oob_size);
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return ERROR_NAND_OPERATION_FAILED;
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}
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{
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/*
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* validate target state
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*/
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int retval;
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retval = validate_target_state(nand);
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if (retval != ERROR_OK)
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return retval;
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}
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{
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int retval = ERROR_OK;
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retval |= imx31_command(nand, NAND_CMD_READ0);
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retval |= imx31_address(nand, 0x00);
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retval |= imx31_address(nand, page & 0xff);
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retval |= imx31_address(nand, (page >> 8) & 0xff);
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if (nand->address_cycles >= 4) {
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retval |= imx31_address(nand, (page >> 16) & 0xff);
|
|
if (nand->address_cycles >= 5) {
|
|
retval |= imx31_address(nand, (page >> 24) & 0xff);
|
|
retval |= imx31_command(nand, NAND_CMD_READSTART);
|
|
}
|
|
}
|
|
retval |= do_data_output(nand);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
if (data) {
|
|
target_read_buffer(target, MX3_NF_MAIN_BUFFER0, data_size,
|
|
data);
|
|
}
|
|
if (oob) {
|
|
target_read_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size,
|
|
oob);
|
|
}
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int test_iomux_settings(struct target *target, uint32_t address,
|
|
uint32_t mask, const char *text)
|
|
{
|
|
uint32_t register_content;
|
|
target_read_u32(target, address, ®ister_content);
|
|
if ((register_content & mask) != (0x12121212 & mask)) {
|
|
LOG_ERROR("IOMUX for {%s} is bad", text);
|
|
return ERROR_FAIL;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int initialize_nf_controller(struct nand_device *nand)
|
|
{
|
|
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
|
|
struct target *target = nand->target;
|
|
/*
|
|
* resets NAND flash controller in zero time ? I don't know.
|
|
*/
|
|
target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
|
|
{
|
|
uint16_t work_mode;
|
|
work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
|
|
if (target->endianness == TARGET_BIG_ENDIAN)
|
|
work_mode |= MX3_NF_BIT_BE_EN;
|
|
if (mx3_nf_info->flags.hw_ecc_enabled)
|
|
work_mode |= MX3_NF_BIT_ECC_EN;
|
|
target_write_u16(target, MX3_NF_CFG1, work_mode);
|
|
}
|
|
/*
|
|
* unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
|
|
*/
|
|
target_write_u16(target, MX3_NF_BUFCFG, 2);
|
|
{
|
|
uint16_t temp;
|
|
target_read_u16(target, MX3_NF_FWP, &temp);
|
|
if ((temp & 0x0007) == 1) {
|
|
LOG_ERROR("NAND flash is tight-locked, reset needed");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
}
|
|
/*
|
|
* unlock NAND flash for write
|
|
*/
|
|
target_write_u16(target, MX3_NF_FWP, 4);
|
|
target_write_u16(target, MX3_NF_LOCKSTART, 0x0000);
|
|
target_write_u16(target, MX3_NF_LOCKEND, 0xFFFF);
|
|
/*
|
|
* 0x0000 means that first SRAM buffer @0xB800_0000 will be used
|
|
*/
|
|
target_write_u16(target, MX3_NF_BUFADDR, 0x0000);
|
|
/*
|
|
* address of SRAM buffer
|
|
*/
|
|
in_sram_address = MX3_NF_MAIN_BUFFER0;
|
|
sign_of_sequental_byte_read = 0;
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
|
|
{
|
|
static uint8_t even_byte;
|
|
/*
|
|
* host-big_endian ??
|
|
*/
|
|
if (sign_of_sequental_byte_read == 0)
|
|
even_byte = 0;
|
|
if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
|
|
LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
|
|
*value = 0;
|
|
sign_of_sequental_byte_read = 0;
|
|
even_byte = 0;
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
} else {
|
|
uint16_t temp;
|
|
target_read_u16(target, in_sram_address, &temp);
|
|
if (even_byte) {
|
|
*value = temp >> 8;
|
|
even_byte = 0;
|
|
in_sram_address += 2;
|
|
} else {
|
|
*value = temp & 0xff;
|
|
even_byte = 1;
|
|
}
|
|
}
|
|
sign_of_sequental_byte_read = 1;
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int get_next_halfword_from_sram_buffer(struct target *target,
|
|
uint16_t *value)
|
|
{
|
|
if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
|
|
LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
|
|
*value = 0;
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
} else {
|
|
target_read_u16(target, in_sram_address, value);
|
|
in_sram_address += 2;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int poll_for_complete_op(struct target *target, const char *text)
|
|
{
|
|
uint16_t poll_complete_status;
|
|
for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
|
|
usleep(25);
|
|
target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
|
|
if (poll_complete_status & MX3_NF_BIT_OP_DONE)
|
|
break;
|
|
}
|
|
if (!(poll_complete_status & MX3_NF_BIT_OP_DONE)) {
|
|
LOG_ERROR("%s sending timeout", text);
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int validate_target_state(struct nand_device *nand)
|
|
{
|
|
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
|
|
struct target *target = nand->target;
|
|
|
|
if (target->state != TARGET_HALTED) {
|
|
LOG_ERROR(target_not_halted_err_msg);
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
|
|
if (mx3_nf_info->flags.target_little_endian !=
|
|
(target->endianness == TARGET_LITTLE_ENDIAN)) {
|
|
/*
|
|
* endianness changed after NAND controller probed
|
|
*/
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int do_data_output(struct nand_device *nand)
|
|
{
|
|
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
|
|
struct target *target = nand->target;
|
|
switch (mx3_nf_info->fin) {
|
|
case MX3_NF_FIN_DATAOUT:
|
|
/*
|
|
* start data output operation (set MX3_NF_BIT_OP_DONE==0)
|
|
*/
|
|
target_write_u16 (target, MX3_NF_CFG2,
|
|
MX3_NF_BIT_DATAOUT_TYPE(mx3_nf_info->optype));
|
|
{
|
|
int poll_result;
|
|
poll_result = poll_for_complete_op(target, "data output");
|
|
if (poll_result != ERROR_OK)
|
|
return poll_result;
|
|
}
|
|
mx3_nf_info->fin = MX3_NF_FIN_NONE;
|
|
/*
|
|
* ECC stuff
|
|
*/
|
|
if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
|
|
&& mx3_nf_info->flags.hw_ecc_enabled) {
|
|
uint16_t ecc_status;
|
|
target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
|
|
switch (ecc_status & 0x000c) {
|
|
case 1 << 2:
|
|
LOG_DEBUG("main area read with 1 (correctable) error");
|
|
break;
|
|
case 2 << 2:
|
|
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
switch (ecc_status & 0x0003) {
|
|
case 1:
|
|
LOG_DEBUG("spare area read with 1 (correctable) error");
|
|
break;
|
|
case 2:
|
|
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
}
|
|
break;
|
|
case MX3_NF_FIN_NONE:
|
|
break;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct nand_flash_controller imx31_nand_flash_controller = {
|
|
.name = "imx31",
|
|
.usage = "nand device imx31 target noecc|hwecc",
|
|
.nand_device_command = &imx31_nand_device_command,
|
|
.init = &imx31_init,
|
|
.reset = &imx31_reset,
|
|
.command = &imx31_command,
|
|
.address = &imx31_address,
|
|
.write_data = &imx31_write_data,
|
|
.read_data = &imx31_read_data,
|
|
.write_page = &imx31_write_page,
|
|
.read_page = &imx31_read_page,
|
|
.nand_ready = &imx31_nand_ready,
|
|
};
|