BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.
This patch also improves reset mechanism. Previous reset mechanism did not
worked properly when slower JTAG adapter was used (it attached too late).
New reset mechanism uses various methods to keep CPU in BootROM, until
the JTAG adapter does not attach again after reset. Additionally,
we trigger SW Reset by directly using DMI commands to write to register
with system bus method, to avoid getting error about unsuccessful write.
The new method works on both FT232H (8MHz JTAG clock) and
unnamed CMSIS-DAP dongle (1.5MHz JTAG clock).
Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8593
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
c986b4dbf2