123 lines
3.8 KiB
INI
123 lines
3.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Source the ESP common configuration file.
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source [find target/esp_common.cfg]
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# Target specific global variables
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set _CHIPNAME "riscv"
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set _CPUTAPID 0x00010c25
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set _ESP_ARCH "riscv"
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set _ONLYCPU 1
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set _ESP_SMP_TARGET 0
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set _ESP_SMP_BREAK 0
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set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844
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# Target specific functions should be implemented for each riscv chips.
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proc riscv_wdt_disable { } {
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# Halt event can occur during config phase (before "init" is done).
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# Ignore it since mww commands don't work at that time.
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if { [string compare [command mode] config] == 0 } {
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return
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}
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# Timer Group 0 & 1 WDTs
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mww 0x60009064 0x50D83AA1
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mww 0x60009048 0
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mww 0x6000A064 0x50D83AA1
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mww 0x6000A048 0
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# WDT_RTC
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#mww 0x600b1c18 0x50D83AA1
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#mww 0x600B1C00 0
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# WDT_SWD
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#mww 0x600b1c20 0x8F1D312A
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#mww 0x600b1c1c 0x84B00000
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}
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proc riscv_soc_reset { } {
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global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0
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riscv dmi_write $_RISCV_DMCONTROL 0x80000001
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riscv dmi_write $_RISCV_SB_CS 0x48000
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riscv dmi_write $_RISCV_SB_ADDR0 0x600b1034
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riscv dmi_write $_RISCV_SB_DATA0 0x80000000
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# clear dmactive to clear sbbusy otherwise debug module gets stuck
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riscv dmi_write $_RISCV_DMCONTROL 0
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riscv dmi_write $_RISCV_SB_CS 0x48000
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riscv dmi_write $_RISCV_SB_ADDR0 0x600b1038
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riscv dmi_write $_RISCV_SB_DATA0 0x10000000
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# clear dmactive to clear sbbusy otherwise debug module gets stuck
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riscv dmi_write $_RISCV_DMCONTROL 0
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riscv dmi_write $_RISCV_DMCONTROL 0x40000001
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# Here debugger reads dmstatus as 0xc03a2
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# Wait for the reset to happen
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sleep 10
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poll
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# Here debugger reads dmstatus as 0x3a2
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# Disable the watchdogs again
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riscv_wdt_disable
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# Here debugger reads anyhalted and allhalted bits as set (0x3a2)
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# We will clean allhalted state by resuming the core.
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riscv dmi_write $_RISCV_DMCONTROL 0x40000001
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# Put the hart back into reset state. Note that we need to keep haltreq set.
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riscv dmi_write $_RISCV_DMCONTROL 0x80000003
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}
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proc riscv_memprot_is_enabled { } {
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global _RISCV_ABS_CMD _RISCV_ABS_DATA0
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# If IRAM/DRAM split is enabled, PMPADDR 5-6 will cover valid IRAM region and PMPADDR 7 will cover valid DRAM region
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# Only TOR mode is used for IRAM and DRAM protections.
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# Read pmpcfg1 and extract into 8-bit variables.
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riscv dmi_write $_RISCV_ABS_CMD 0x2203a1
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set pmpcfg1 [riscv dmi_read $_RISCV_ABS_DATA0]
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set pmp5cfg [expr {($pmpcfg1 >> (8 * 1)) & 0xFF}]
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set pmp6cfg [expr {($pmpcfg1 >> (8 * 2)) & 0xFF}]
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set pmp7cfg [expr {($pmpcfg1 >> (8 * 3)) & 0xFF}]
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# Read PMPADDR 5-7
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riscv dmi_write $_RISCV_ABS_CMD 0x2203b5
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set pmpaddr5 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
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riscv dmi_write $_RISCV_ABS_CMD 0x2203b6
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set pmpaddr6 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
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riscv dmi_write $_RISCV_ABS_CMD 0x2203b7
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set pmpaddr7 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
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set IRAM_LOW 0x40800000
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set IRAM_HIGH 0x40850000
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set DRAM_LOW 0x40800000
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set DRAM_HIGH 0x40850000
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set PMP_RWX 0x07
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set PMP_RW 0x03
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# The lock bit remains unset during the execution of the 2nd stage bootloader.
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# Thus, we do not perform a lock bit check for IRAM and DRAM regions.
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# Check OpenOCD can write and execute from IRAM.
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if {$pmpaddr5 >= $IRAM_LOW && $pmpaddr6 <= $IRAM_HIGH} {
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if {($pmp5cfg & $PMP_RWX) != 0 || ($pmp6cfg & $PMP_RWX) != $PMP_RWX} {
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return 1
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}
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}
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# Check OpenOCD can read/write entire DRAM region.
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# If IRAM/DRAM split is disabled, pmpaddr7 will be zero, checking only IRAM region is enough.
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if {$pmpaddr7 != 0 && $pmpaddr7 >= $DRAM_LOW && $pmpaddr7 <= $DRAM_HIGH} {
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if {($pmp7cfg & $PMP_RW) != $PMP_RW} {
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return 1
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}
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}
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return 0
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}
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create_esp_target $_ESP_ARCH
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