* Align algorithm stack to XLEN.
This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.
Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d
* Compile 32-bit RISC-V algorithms for RV32E.
Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa
* Remove debug code.
Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b
* Dump start of gdb packets escaping non-printable.
Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915
* Propagate flash programming errors.
Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7
* Improve debug messaging.
Change-Id: I47ac3518f3b241986c677824864102936100adf6
* Add debug output to flash image.
This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.
Change-Id: Id44c6498c288872cc2cec79044116ac38198c572
* Make timeout depend on how much data is written.
Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e
* Fix issi erase commands.
This is required to flash HiFive Unleashed.
Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10
* Fix running algorithm on multicore `-rtos riscv`.
The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.
Change-Id: I140431898285cf471b372139cef2378ab4879377
* Make fespi flash algorithm debugging optional.
Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.
Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
274be9587f