52 lines
1.3 KiB
INI
52 lines
1.3 KiB
INI
# Freescale i.MX51
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME imx51
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}
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# CoreSight Debug Access Port
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x1ba00477
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}
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jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_DAP_TAPID
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# SDMA / no IDCODE
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jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
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# SJC
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if { [info exists SJC_TAPID] } {
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set _SJC_TAPID SJC_TAPID
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} else {
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set _SJC_TAPID 0x0190c01d
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}
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jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
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-expected-id $_SJC_TAPID -ignore-version
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# GDB target: Cortex-A8, using DAP
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
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# some TCK tycles are required to activate the DEBUG power domain
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jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
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# have the DAP "always" be active
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jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
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proc imx51_dbginit {target} {
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# General Cortex A8 debug initialisation
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cortex_a8 dbginit
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}
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# Slow speed to be sure it will work
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jtag_rclk 1000
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$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
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$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"
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