120 lines
4.4 KiB
C
120 lines
4.4 KiB
C
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/***************************************************************************
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* Copyright (C) 2009 by Alexei Babich *
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* Rezonans plc., Chelyabinsk, Russia *
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* impatt@mail.ru *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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/*
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* Freescale iMX2* OpenOCD NAND Flash controller support.
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* based on Freescale iMX3* OpenOCD NAND Flash controller support.
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*
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* Many thanks to Ben Dooks for writing s3c24xx driver.
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*/
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#define MX2_NF_BASE_ADDR 0xd8000000
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#define MX2_NF_BUFSIZ (MX2_NF_BASE_ADDR + 0xe00)
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#define MX2_NF_BUFADDR (MX2_NF_BASE_ADDR + 0xe04)
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#define MX2_NF_FADDR (MX2_NF_BASE_ADDR + 0xe06)
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#define MX2_NF_FCMD (MX2_NF_BASE_ADDR + 0xe08)
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#define MX2_NF_BUFCFG (MX2_NF_BASE_ADDR + 0xe0a)
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#define MX2_NF_ECCSTATUS (MX2_NF_BASE_ADDR + 0xe0c)
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#define MX2_NF_ECCMAINPOS (MX2_NF_BASE_ADDR + 0xe0e)
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#define MX2_NF_ECCSPAREPOS (MX2_NF_BASE_ADDR + 0xe10)
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#define MX2_NF_FWP (MX2_NF_BASE_ADDR + 0xe12)
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#define MX2_NF_LOCKSTART (MX2_NF_BASE_ADDR + 0xe14)
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#define MX2_NF_LOCKEND (MX2_NF_BASE_ADDR + 0xe16)
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#define MX2_NF_FWPSTATUS (MX2_NF_BASE_ADDR + 0xe18)
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/*
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* all bits not marked as self-clearing bit
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*/
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#define MX2_NF_CFG1 (MX2_NF_BASE_ADDR + 0xe1a)
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#define MX2_NF_CFG2 (MX2_NF_BASE_ADDR + 0xe1c)
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#define MX2_NF_MAIN_BUFFER0 (MX2_NF_BASE_ADDR + 0x0000)
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#define MX2_NF_MAIN_BUFFER1 (MX2_NF_BASE_ADDR + 0x0200)
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#define MX2_NF_MAIN_BUFFER2 (MX2_NF_BASE_ADDR + 0x0400)
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#define MX2_NF_MAIN_BUFFER3 (MX2_NF_BASE_ADDR + 0x0600)
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#define MX2_NF_SPARE_BUFFER0 (MX2_NF_BASE_ADDR + 0x0800)
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#define MX2_NF_SPARE_BUFFER1 (MX2_NF_BASE_ADDR + 0x0810)
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#define MX2_NF_SPARE_BUFFER2 (MX2_NF_BASE_ADDR + 0x0820)
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#define MX2_NF_SPARE_BUFFER3 (MX2_NF_BASE_ADDR + 0x0830)
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#define MX2_NF_MAIN_BUFFER_LEN 512
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#define MX2_NF_SPARE_BUFFER_LEN 16
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#define MX2_NF_LAST_BUFFER_ADDR ((MX2_NF_SPARE_BUFFER3) + MX2_NF_SPARE_BUFFER_LEN - 2)
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/* bits in MX2_NF_CFG1 register */
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#define MX2_NF_BIT_SPARE_ONLY_EN (1<<2)
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#define MX2_NF_BIT_ECC_EN (1<<3)
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#define MX2_NF_BIT_INT_DIS (1<<4)
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#define MX2_NF_BIT_BE_EN (1<<5)
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#define MX2_NF_BIT_RESET_EN (1<<6)
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#define MX2_NF_BIT_FORCE_CE (1<<7)
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/* bits in MX2_NF_CFG2 register */
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/*Flash Command Input*/
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#define MX2_NF_BIT_OP_FCI (1<<0)
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/*
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* Flash Address Input
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*/
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#define MX2_NF_BIT_OP_FAI (1<<1)
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/*
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* Flash Data Input
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*/
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#define MX2_NF_BIT_OP_FDI (1<<2)
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/* see "enum mx_dataout_type" below */
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#define MX2_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
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#define MX2_NF_BIT_OP_DONE (1<<15)
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#define MX2_CCM_CGR2 0x53f80028
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#define MX2_GPR 0x43fac008
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//#define MX2_PCSR 0x53f8000c
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#define MX2_FMCR 0x10027814
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#define MX2_FMCR_NF_16BIT_SEL (1<<4)
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#define MX2_FMCR_NF_FMS (1<<5)
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enum mx_dataout_type
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{
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MX2_NF_DATAOUT_PAGE = 1,
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MX2_NF_DATAOUT_NANDID = 2,
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MX2_NF_DATAOUT_NANDSTATUS = 4,
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};
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enum mx_nf_finalize_action
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{
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MX2_NF_FIN_NONE,
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MX2_NF_FIN_DATAOUT,
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};
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struct mx2_nf_flags
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{
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unsigned host_little_endian:1;
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unsigned target_little_endian:1;
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unsigned nand_readonly:1;
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unsigned one_kb_sram:1;
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unsigned hw_ecc_enabled:1;
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};
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struct mx2_nf_controller
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{
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enum mx_dataout_type optype;
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enum mx_nf_finalize_action fin;
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struct mx2_nf_flags flags;
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};
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