riscv-openocd/src/target/riscv
Tim Newsome 6f3daf38c7
Fix small memory leak. (#672)
Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-01-27 10:00:06 -08:00
..
Makefile.am Add RISC-V support. 2018-07-24 13:07:26 +01:00
asm.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
batch.c Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
batch.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
debug_defines.h riscv: Regenerated debug_defines.h and encoding.h 2021-11-20 14:39:13 +00:00
encoding.h riscv: Regenerated debug_defines.h and encoding.h 2021-11-20 14:39:13 +00:00
gdb_regs.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
opcodes.h Properly save/restore vtype.ill (#661) 2021-11-12 11:29:00 -08:00
program.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
program.h Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
riscv-011.c Merge branch 'master' into from_upstream 2021-10-25 10:20:31 -07:00
riscv-013.c Fix small memory leak. (#672) 2022-01-27 10:00:06 -08:00
riscv.c target/riscv: calloc() memory per register. 2021-12-24 15:10:20 +00:00
riscv.h target/riscv: calloc() memory per register. 2021-12-24 15:10:20 +00:00
riscv_semihosting.c Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00