riscv-openocd/src/target/riscv
Tim Newsome b68674a1da Upstream tons of RISC-V changes.
These are all the changes from https://github.com/riscv/riscv-openocd
(approximately 91dc0c0c) made just to src/target/riscv/*. Some of the
new code is disabled because it requires some other target-independent
changes which I didn't want to include here.

Built like this, OpenOCD passes:
* All single-RV32 tests against spike.
* All single-RV64 tests against spike.
* Enough HiFive1 tests. (I suspect the failures are due to the test
suite rotting.)
* Many dual-RV32 (-rtos hwthread) against spike.
* Many dual-RV64 (-rtos hwthread) against spike.

I suspect this is an overall improvement compared to what's in mainline
right now, and it gets me a lot closer to getting all the riscv-openocd
work upstreamed.

Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5821
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2020-10-14 05:43:05 +01:00
..
Makefile.am Add RISC-V support. 2018-07-24 13:07:26 +01:00
asm.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
batch.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
batch.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
debug_defines.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
encoding.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
gdb_regs.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
opcodes.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
program.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
program.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
riscv-011.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
riscv-013.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
riscv.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
riscv.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
riscv_semihosting.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00