136 lines
4.1 KiB
C
136 lines
4.1 KiB
C
/*
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* Copyright (C) 2009 by Marvell Semiconductors, Inc.
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* Written by Nicolas Pitre <nico at marvell.com>
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*
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* Copyright (C) 2009 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "arm_nandio.h"
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#include "armv4_5.h"
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#include "algorithm.h"
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/*
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* ARM-specific bulk write from buffer to address of 8-bit wide NAND.
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* For now this only supports ARMv4 and ARMv5 cores.
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*
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* Enhancements to target_run_algorithm() could enable:
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* - ARMv6 and ARMv7 cores in ARM mode
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*
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* Different code fragments could handle:
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* - Thumb2 cores like Cortex-M (needs different byteswapping)
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* - 16-bit wide data (needs different setup too)
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*/
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int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
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{
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struct target *target = nand->target;
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struct armv4_5_algorithm algo;
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struct arm *armv4_5 = target->arch_info;
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struct reg_param reg_params[3];
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uint32_t target_buf;
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uint32_t exit = 0;
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int retval;
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/* Inputs:
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* r0 NAND data address (byte wide)
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* r1 buffer address
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* r2 buffer length
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*/
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static const uint32_t code[] = {
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0xe4d13001, /* s: ldrb r3, [r1], #1 */
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0xe5c03000, /* strb r3, [r0] */
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0xe2522001, /* subs r2, r2, #1 */
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0x1afffffb, /* bne s */
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/* exit: ARMv4 needs hardware breakpoint */
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0xe1200070, /* e: bkpt #0 */
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};
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if (!nand->copy_area) {
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uint8_t code_buf[sizeof(code)];
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unsigned i;
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/* make sure we have a working area */
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if (target_alloc_working_area(target,
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sizeof(code) + nand->chunk_size,
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&nand->copy_area) != ERROR_OK) {
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LOG_DEBUG("%s: no %d byte buffer",
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__FUNCTION__,
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(int) sizeof(code) + nand->chunk_size);
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return ERROR_NAND_NO_BUFFER;
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}
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/* buffer code in target endianness */
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for (i = 0; i < sizeof(code) / 4; i++)
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target_buffer_set_u32(target, code_buf + i * 4, code[i]);
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/* copy code to work area */
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retval = target_write_memory(target,
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nand->copy_area->address,
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4, sizeof(code) / 4, code_buf);
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if (retval != ERROR_OK)
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return retval;
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}
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/* copy data to work area */
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target_buf = nand->copy_area->address + sizeof(code);
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retval = target_bulk_write_memory(target, target_buf, size / 4, data);
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if (retval == ERROR_OK && (size & 3) != 0)
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retval = target_write_memory(target,
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target_buf + (size & ~3),
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1, size & 3, data + (size & ~3));
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if (retval != ERROR_OK)
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return retval;
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/* set up algorithm and parameters */
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algo.common_magic = ARMV4_5_COMMON_MAGIC;
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algo.core_mode = ARMV4_5_MODE_SVC;
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algo.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_IN);
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init_reg_param(®_params[1], "r1", 32, PARAM_IN);
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init_reg_param(®_params[2], "r2", 32, PARAM_IN);
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buf_set_u32(reg_params[0].value, 0, 32, nand->data);
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buf_set_u32(reg_params[1].value, 0, 32, target_buf);
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buf_set_u32(reg_params[2].value, 0, 32, size);
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/* armv4 must exit using a hardware breakpoint */
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if (armv4_5->is_armv4)
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exit = nand->copy_area->address + sizeof(code) - 4;
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/* use alg to write data from work area to NAND chip */
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retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
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nand->copy_area->address, exit, 1000, &algo);
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if (retval != ERROR_OK)
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LOG_ERROR("error executing hosted NAND write");
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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return retval;
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}
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/* REVISIT do the same for bulk *read* too ... */
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