500 lines
16 KiB
C
500 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Xtensa application tracing module for OpenOCD *
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* Copyright (C) 2017 Espressif Systems Ltd. *
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***************************************************************************/
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/*
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How it works?
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https://github.com/espressif/esp-idf/blob/master/components/app_trace/port/xtensa/port.c#L8
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/align.h>
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#include <target/xtensa/xtensa.h>
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#include <target/xtensa/xtensa_debug_module.h>
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#include "esp_xtensa_apptrace.h"
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/* TRAX is disabled, so we use its registers for our own purposes
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* | 31..XXXXXX..24 | 23 .(host_connect). 23 | 22 .(host_data). 22| 21..(block_id)..15 | 14..(block_len)..0 |
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*/
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#define XTENSA_APPTRACE_CTRL_REG XDMREG_DELAYCNT
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#define XTENSA_APPTRACE_BLOCK_ID_MSK 0x7FUL
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#define XTENSA_APPTRACE_BLOCK_ID_MAX XTENSA_APPTRACE_BLOCK_ID_MSK
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/* if non-zero then apptrace code entered the critical section and the value is an address of the
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* critical section's exit point */
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#define XTENSA_APPTRACE_STAT_REG XDMREG_TRIGGERPC
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#define XTENSA_APPTRACE_BLOCK_LEN_MSK 0x7FFFUL
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#define XTENSA_APPTRACE_BLOCK_LEN(_l_) ((_l_) & XTENSA_APPTRACE_BLOCK_LEN_MSK)
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#define XTENSA_APPTRACE_BLOCK_LEN_GET(_v_) ((_v_) & XTENSA_APPTRACE_BLOCK_LEN_MSK)
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#define XTENSA_APPTRACE_BLOCK_ID(_id_) (((_id_) & XTENSA_APPTRACE_BLOCK_ID_MSK) << 15)
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#define XTENSA_APPTRACE_BLOCK_ID_GET(_v_) (((_v_) >> 15) & XTENSA_APPTRACE_BLOCK_ID_MSK)
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#define XTENSA_APPTRACE_HOST_DATA BIT(22)
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#define XTENSA_APPTRACE_HOST_CONNECT BIT(23)
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static int esp_xtensa_apptrace_leave_crit_section_start(struct target *target);
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static int esp_xtensa_apptrace_leave_crit_section_stop(struct target *target);
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static int esp_xtensa_apptrace_buffs_write(struct target *target,
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uint32_t bufs_num,
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uint32_t buf_sz[],
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const uint8_t *bufs[],
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uint32_t block_id,
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bool ack,
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bool data);
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struct esp32_apptrace_hw esp_xtensa_apptrace_hw = {
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.max_block_id = XTENSA_APPTRACE_BLOCK_ID_MAX,
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.max_block_size_get = esp_xtensa_apptrace_block_max_size_get,
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.status_reg_read = esp_xtensa_apptrace_status_reg_read,
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.ctrl_reg_write = esp_xtensa_apptrace_ctrl_reg_write,
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.ctrl_reg_read = esp_xtensa_apptrace_ctrl_reg_read,
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.data_len_read = esp_xtensa_apptrace_data_len_read,
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.data_read = esp_xtensa_apptrace_data_read,
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.usr_block_max_size_get = esp_xtensa_apptrace_usr_block_max_size_get,
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.buffs_write = esp_xtensa_apptrace_buffs_write,
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.leave_trace_crit_section_start = esp_xtensa_apptrace_leave_crit_section_start,
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.leave_trace_crit_section_stop = esp_xtensa_apptrace_leave_crit_section_stop,
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};
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uint32_t esp_xtensa_apptrace_block_max_size_get(struct target *target)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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struct xtensa_trace_status trace_status;
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struct xtensa_trace_config trace_config;
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uint32_t max_trace_block_sz;
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int res = xtensa_dm_trace_status_read(&xtensa->dbg_mod, &trace_status);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to read TRAX status (%d)!", res);
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return 0;
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}
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max_trace_block_sz = BIT(((trace_status.stat >> 8) & 0x1f) - 2) * 4;
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res = xtensa_dm_trace_config_read(&xtensa->dbg_mod, &trace_config);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to read TRAX config (%d)!", res);
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return 0;
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}
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LOG_DEBUG("ctrl=0x%" PRIx32 " memadrstart=0x%" PRIx32 " memadrend=0x%" PRIx32 " traxadr=0x%" PRIx32,
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trace_config.ctrl,
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trace_config.memaddr_start,
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trace_config.memaddr_end,
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trace_config.addr);
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return max_trace_block_sz;
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}
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uint32_t esp_xtensa_apptrace_usr_block_max_size_get(struct target *target)
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{
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return esp_xtensa_apptrace_block_max_size_get(target) - sizeof(struct esp_apptrace_host2target_hdr);
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}
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int esp_xtensa_apptrace_data_len_read(struct target *target,
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uint32_t *block_id,
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uint32_t *len)
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{
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return esp_xtensa_apptrace_ctrl_reg_read(target, block_id, len, NULL);
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}
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int esp_xtensa_apptrace_usr_block_write(struct target *target,
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uint32_t block_id,
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const uint8_t *data,
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uint32_t size)
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{
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return esp_apptrace_usr_block_write(&esp_xtensa_apptrace_hw, target, block_id, data, size);
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}
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static int esp_xtensa_apptrace_data_reverse_read(struct xtensa *xtensa,
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uint32_t size,
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uint8_t *buffer,
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uint8_t *unal_bytes)
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{
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int res = 0;
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uint32_t rd_sz = ALIGN_UP(size, 4);
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res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, (xtensa->core_config->trace.mem_sz - rd_sz) / 4);
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if (res != ERROR_OK)
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return res;
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if (!IS_ALIGNED(size, 4)) {
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res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, unal_bytes);
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if (res != ERROR_OK)
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return res;
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}
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for (unsigned int i = size / 4; i != 0; i--) {
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res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, &buffer[(i - 1) * 4]);
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if (res != ERROR_OK)
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return res;
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}
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return ERROR_OK;
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}
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static int esp_xtensa_apptrace_data_normal_read(struct xtensa *xtensa,
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uint32_t size,
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uint8_t *buffer,
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uint8_t *unal_bytes)
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{
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int res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, 0);
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if (res != ERROR_OK)
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return res;
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for (unsigned int i = 0; i < size / 4; i++) {
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res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, &buffer[i * 4]);
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if (res != ERROR_OK)
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return res;
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}
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if (!IS_ALIGNED(size, 4)) {
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res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, unal_bytes);
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if (res != ERROR_OK)
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return res;
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}
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return ERROR_OK;
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}
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int esp_xtensa_apptrace_data_read(struct target *target,
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uint32_t size,
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uint8_t *buffer,
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uint32_t block_id,
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bool ack)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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int res;
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uint32_t tmp = XTENSA_APPTRACE_HOST_CONNECT | XTENSA_APPTRACE_BLOCK_ID(block_id) |
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XTENSA_APPTRACE_BLOCK_LEN(0);
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uint8_t unal_bytes[4];
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LOG_DEBUG("Read data on target (%s)", target_name(target));
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if (xtensa->core_config->trace.reversed_mem_access)
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res = esp_xtensa_apptrace_data_reverse_read(xtensa, size, buffer, unal_bytes);
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else
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res = esp_xtensa_apptrace_data_normal_read(xtensa, size, buffer, unal_bytes);
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if (res != ERROR_OK)
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return res;
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if (ack) {
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LOG_DEBUG("Ack block %" PRIu32 " target (%s)!", block_id, target_name(target));
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res = xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
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if (res != ERROR_OK)
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return res;
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}
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xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
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res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to exec JTAG queue!");
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return res;
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}
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if (!IS_ALIGNED(size, 4)) {
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/* copy the last unaligned bytes */
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memcpy(buffer + ALIGN_DOWN(size, 4), unal_bytes, size & 0x3UL);
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}
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return ERROR_OK;
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}
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int esp_xtensa_apptrace_ctrl_reg_write(struct target *target,
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uint32_t block_id,
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uint32_t len,
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bool conn,
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bool data)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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uint32_t tmp = (conn ? XTENSA_APPTRACE_HOST_CONNECT : 0) |
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(data ? XTENSA_APPTRACE_HOST_DATA : 0) | XTENSA_APPTRACE_BLOCK_ID(block_id) |
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XTENSA_APPTRACE_BLOCK_LEN(len);
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xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
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xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
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int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to exec JTAG queue!");
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return res;
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}
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return ERROR_OK;
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}
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int esp_xtensa_apptrace_ctrl_reg_read(struct target *target,
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uint32_t *block_id,
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uint32_t *len,
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bool *conn)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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uint8_t tmp[4];
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xtensa_queue_dbg_reg_read(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
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xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
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int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
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if (res != ERROR_OK)
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return res;
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uint32_t val = target_buffer_get_u32(target, tmp);
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if (block_id)
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*block_id = XTENSA_APPTRACE_BLOCK_ID_GET(val);
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if (len)
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*len = XTENSA_APPTRACE_BLOCK_LEN_GET(val);
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if (conn)
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*conn = val & XTENSA_APPTRACE_HOST_CONNECT;
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return ERROR_OK;
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}
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int esp_xtensa_apptrace_status_reg_read(struct target *target, uint32_t *stat)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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uint8_t tmp[4];
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int res = xtensa_queue_dbg_reg_read(xtensa, XTENSA_APPTRACE_STAT_REG, tmp);
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if (res != ERROR_OK)
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return res;
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xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
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res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to exec JTAG queue!");
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return res;
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}
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*stat = buf_get_u32(tmp, 0, 32);
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return ERROR_OK;
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}
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int esp_xtensa_apptrace_status_reg_write(struct target *target, uint32_t stat)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_STAT_REG, stat);
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xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
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int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to exec JTAG queue!");
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return res;
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}
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return ERROR_OK;
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}
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static int esp_xtensa_swdbg_activate(struct target *target, int enab)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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xtensa_queue_dbg_reg_write(xtensa, enab ? XDMREG_DCRSET : XDMREG_DCRCLR, OCDDCR_DEBUGSWACTIVE);
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xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
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int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
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if (res != ERROR_OK) {
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LOG_ERROR("%s: writing DCR failed!", target->cmd_name);
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return res;
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}
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return ERROR_OK;
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}
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static int esp_xtensa_apptrace_leave_crit_section_start(struct target *target)
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{
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/* TODO: not sure that we need this, but it seems that we fail to leave tracing critical
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*section w/o this */
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int res = esp_xtensa_swdbg_activate(target, 1 /*enable*/);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to activate SW debug (%d)!", res);
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return res;
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}
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return ERROR_OK;
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}
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static int esp_xtensa_apptrace_leave_crit_section_stop(struct target *target)
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{
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int res = esp_xtensa_swdbg_activate(target, 0 /*disable*/);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to activate SW debug (%d)!", res);
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return res;
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}
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return ERROR_OK;
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}
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static int esp_xtensa_apptrace_queue_reverse_write(struct target *target, uint32_t bufs_num,
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uint32_t buf_sz[], const uint8_t *bufs[])
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{
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int res = ERROR_OK;
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uint32_t cached_bytes = 0, total_sz = 0;
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uint8_t cached_data8[sizeof(uint32_t)] = { 0 };
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uint32_t cached_data32 = 0;
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struct xtensa *xtensa = target_to_xtensa(target);
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for (uint32_t i = 0; i < bufs_num; i++)
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total_sz += buf_sz[i];
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if (!IS_ALIGNED(total_sz, 4)) {
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cached_bytes = sizeof(uint32_t) - (total_sz & 0x3UL);
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total_sz = ALIGN_UP(total_sz, 4);
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}
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xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, (xtensa->core_config->trace.mem_sz - total_sz) / 4);
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for (uint32_t i = bufs_num; i > 0; i--) {
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uint32_t bsz = buf_sz[i - 1];
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const uint8_t *cur_buf = &bufs[i - 1][bsz];
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uint32_t bytes_to_cache;
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/* if there are cached bytes from the previous buffer, combine them with the last
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* from the current buffer */
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if (cached_bytes) {
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if ((cached_bytes + bsz) < sizeof(uint32_t))
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bytes_to_cache = bsz;
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else
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bytes_to_cache = sizeof(uint32_t) - cached_bytes;
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memcpy(&cached_data8[sizeof(uint32_t) - cached_bytes - bytes_to_cache],
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cur_buf - bytes_to_cache,
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bytes_to_cache);
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cached_data32 = target_buffer_get_u32(target, cached_data8);
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cached_bytes += bytes_to_cache;
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if (cached_bytes < sizeof(uint32_t))
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continue;
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res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
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if (res != ERROR_OK)
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return res;
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bsz -= bytes_to_cache;
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cur_buf -= bytes_to_cache;
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memset(cached_data8, 0x00, sizeof(cached_data8));
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cached_bytes = 0;
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}
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/* write full dwords */
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for (unsigned int k = bsz; k >= sizeof(uint32_t); k -= sizeof(uint32_t)) {
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uint32_t temp = target_buffer_get_u32(target, cur_buf - sizeof(uint32_t));
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res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, temp);
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if (res != ERROR_OK)
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return res;
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cur_buf -= sizeof(uint32_t);
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}
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/* if there are bytes to be cached (1..3) */
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bytes_to_cache = bsz & 0x3UL;
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if (bytes_to_cache > 0) {
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if (bytes_to_cache + cached_bytes >= sizeof(uint32_t)) {
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/* filling the cache buffer from the end to beginning */
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uint32_t to_copy = sizeof(uint32_t) - cached_bytes;
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memcpy(&cached_data8[0], cur_buf - to_copy, to_copy);
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cached_data32 = target_buffer_get_u32(target, cached_data8);
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/* write full word of cached bytes */
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res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
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if (res != ERROR_OK)
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return res;
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/* cache remaining bytes */
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memset(cached_data8, 0x00, sizeof(cached_data8));
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cur_buf -= to_copy;
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to_copy = bytes_to_cache + cached_bytes - sizeof(uint32_t);
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memcpy(&cached_data8[sizeof(uint32_t) - to_copy], cur_buf - to_copy, to_copy);
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cached_bytes = to_copy;
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} else {
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/* filling the cache buffer from the end to beginning */
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memcpy(&cached_data8[sizeof(uint32_t) - cached_bytes - bytes_to_cache],
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cur_buf - bytes_to_cache,
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bytes_to_cache);
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cached_bytes += bytes_to_cache;
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}
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}
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}
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return ERROR_OK;
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}
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static int esp_xtensa_apptrace_queue_normal_write(struct target *target, uint32_t bufs_num,
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uint32_t buf_sz[], const uint8_t *bufs[])
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{
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int res = ERROR_OK;
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uint32_t cached_bytes = 0;
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uint8_t cached_data8[4] = { 0 };
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uint32_t cached_data32 = 0;
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struct xtensa *xtensa = target_to_xtensa(target);
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/* | 1 | 2 | 1 | 2 | 4 |.......|
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* | 4 | 4 | 4 | */
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xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, 0);
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for (unsigned int i = 0; i < bufs_num; i++) {
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uint32_t bsz = buf_sz[i];
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const uint8_t *cur_buf = bufs[i];
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uint32_t bytes_to_cache;
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/* if there are cached bytes from the previous buffer, combine them with the last
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* from the current buffer */
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if (cached_bytes) {
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if ((cached_bytes + bsz) < sizeof(uint32_t))
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bytes_to_cache = bsz;
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else
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bytes_to_cache = sizeof(uint32_t) - cached_bytes;
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memcpy(&cached_data8[cached_bytes], cur_buf, bytes_to_cache);
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cached_bytes += bytes_to_cache;
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if (cached_bytes < sizeof(uint32_t))
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continue;
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cached_data32 = target_buffer_get_u32(target, cached_data8);
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res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
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if (res != ERROR_OK)
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return res;
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bsz -= bytes_to_cache;
|
|
cur_buf += bytes_to_cache;
|
|
memset(cached_data8, 0x00, sizeof(cached_data8));
|
|
cached_bytes = 0;
|
|
}
|
|
/* write full dwords */
|
|
for (unsigned int k = 0; (k + sizeof(uint32_t)) <= bsz; k += sizeof(uint32_t)) {
|
|
uint32_t temp = target_buffer_get_u32(target, cur_buf);
|
|
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, temp);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
cur_buf += sizeof(uint32_t);
|
|
}
|
|
/* if there are bytes to be cached (1..3) */
|
|
bytes_to_cache = bsz & 0x3UL;
|
|
if (bytes_to_cache > 0) {
|
|
if (bytes_to_cache + cached_bytes >= sizeof(uint32_t)) {
|
|
memcpy(&cached_data8[0], cur_buf, sizeof(uint32_t) - cached_bytes);
|
|
cached_data32 = target_buffer_get_u32(target, cached_data8);
|
|
/* write full word of cached bytes */
|
|
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
/* cache remaining bytes */
|
|
memset(cached_data8, 0x00, sizeof(cached_data8));
|
|
cur_buf += sizeof(uint32_t) - cached_bytes;
|
|
cached_bytes = bytes_to_cache + cached_bytes - sizeof(uint32_t);
|
|
memcpy(&cached_data8[0], cur_buf, cached_bytes);
|
|
} else {
|
|
memcpy(&cached_data8[cached_bytes], cur_buf, bytes_to_cache);
|
|
cached_bytes += bytes_to_cache;
|
|
}
|
|
}
|
|
}
|
|
if (cached_bytes) {
|
|
/* write remaining cached bytes */
|
|
cached_data32 = target_buffer_get_u32(target, cached_data8);
|
|
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int esp_xtensa_apptrace_buffs_write(struct target *target,
|
|
uint32_t bufs_num,
|
|
uint32_t buf_sz[],
|
|
const uint8_t *bufs[],
|
|
uint32_t block_id,
|
|
bool ack,
|
|
bool data)
|
|
{
|
|
struct xtensa *xtensa = target_to_xtensa(target);
|
|
int res = ERROR_OK;
|
|
uint32_t tmp = XTENSA_APPTRACE_HOST_CONNECT |
|
|
(data ? XTENSA_APPTRACE_HOST_DATA : 0) | XTENSA_APPTRACE_BLOCK_ID(block_id) |
|
|
XTENSA_APPTRACE_BLOCK_LEN(0);
|
|
|
|
if (xtensa->core_config->trace.reversed_mem_access)
|
|
res = esp_xtensa_apptrace_queue_reverse_write(target, bufs_num, buf_sz, bufs);
|
|
else
|
|
res = esp_xtensa_apptrace_queue_normal_write(target, bufs_num, buf_sz, bufs);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
if (ack) {
|
|
LOG_DEBUG("Ack block %" PRId32 " on target (%s)!", block_id, target_name(target));
|
|
res = xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
}
|
|
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
|
|
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to exec JTAG queue!");
|
|
return res;
|
|
}
|
|
return ERROR_OK;
|
|
}
|