102 lines
3.2 KiB
C
102 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2009 by Alexei Babich *
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* Rezonans plc., Chelyabinsk, Russia *
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* impatt@mail.ru *
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***************************************************************************/
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#ifndef OPENOCD_FLASH_NAND_MX3_H
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#define OPENOCD_FLASH_NAND_MX3_H
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/*
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* Freescale iMX3* OpenOCD NAND Flash controller support.
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*
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* Many thanks to Ben Dooks for writing s3c24xx driver.
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*/
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#define MX3_NF_BASE_ADDR 0xb8000000
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#define MX3_NF_BUFSIZ (MX3_NF_BASE_ADDR + 0xe00)
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#define MX3_NF_BUFADDR (MX3_NF_BASE_ADDR + 0xe04)
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#define MX3_NF_FADDR (MX3_NF_BASE_ADDR + 0xe06)
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#define MX3_NF_FCMD (MX3_NF_BASE_ADDR + 0xe08)
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#define MX3_NF_BUFCFG (MX3_NF_BASE_ADDR + 0xe0a)
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#define MX3_NF_ECCSTATUS (MX3_NF_BASE_ADDR + 0xe0c)
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#define MX3_NF_ECCMAINPOS (MX3_NF_BASE_ADDR + 0xe0e)
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#define MX3_NF_ECCSPAREPOS (MX3_NF_BASE_ADDR + 0xe10)
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#define MX3_NF_FWP (MX3_NF_BASE_ADDR + 0xe12)
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#define MX3_NF_LOCKSTART (MX3_NF_BASE_ADDR + 0xe14)
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#define MX3_NF_LOCKEND (MX3_NF_BASE_ADDR + 0xe16)
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#define MX3_NF_FWPSTATUS (MX3_NF_BASE_ADDR + 0xe18)
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/*
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* all bits not marked as self-clearing bit
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*/
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#define MX3_NF_CFG1 (MX3_NF_BASE_ADDR + 0xe1a)
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#define MX3_NF_CFG2 (MX3_NF_BASE_ADDR + 0xe1c)
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#define MX3_NF_MAIN_BUFFER0 (MX3_NF_BASE_ADDR + 0x0000)
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#define MX3_NF_MAIN_BUFFER1 (MX3_NF_BASE_ADDR + 0x0200)
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#define MX3_NF_MAIN_BUFFER2 (MX3_NF_BASE_ADDR + 0x0400)
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#define MX3_NF_MAIN_BUFFER3 (MX3_NF_BASE_ADDR + 0x0600)
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#define MX3_NF_SPARE_BUFFER0 (MX3_NF_BASE_ADDR + 0x0800)
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#define MX3_NF_SPARE_BUFFER1 (MX3_NF_BASE_ADDR + 0x0810)
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#define MX3_NF_SPARE_BUFFER2 (MX3_NF_BASE_ADDR + 0x0820)
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#define MX3_NF_SPARE_BUFFER3 (MX3_NF_BASE_ADDR + 0x0830)
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#define MX3_NF_MAIN_BUFFER_LEN 512
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#define MX3_NF_SPARE_BUFFER_LEN 16
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#define MX3_NF_LAST_BUFFER_ADDR ((MX3_NF_SPARE_BUFFER3) + MX3_NF_SPARE_BUFFER_LEN - 2)
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/* bits in MX3_NF_CFG1 register */
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#define MX3_NF_BIT_SPARE_ONLY_EN (1<<2)
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#define MX3_NF_BIT_ECC_EN (1<<3)
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#define MX3_NF_BIT_INT_DIS (1<<4)
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#define MX3_NF_BIT_BE_EN (1<<5)
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#define MX3_NF_BIT_RESET_EN (1<<6)
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#define MX3_NF_BIT_FORCE_CE (1<<7)
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/* bits in MX3_NF_CFG2 register */
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/*Flash Command Input*/
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#define MX3_NF_BIT_OP_FCI (1<<0)
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/*
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* Flash Address Input
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*/
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#define MX3_NF_BIT_OP_FAI (1<<1)
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/*
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* Flash Data Input
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*/
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#define MX3_NF_BIT_OP_FDI (1<<2)
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/* see "enum mx_dataout_type" below */
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#define MX3_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
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#define MX3_NF_BIT_OP_DONE (1<<15)
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#define MX3_CCM_CGR2 0x53f80028
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#define MX3_GPR 0x43fac008
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#define MX3_PCSR 0x53f8000c
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enum mx_dataout_type {
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MX3_NF_DATAOUT_PAGE = 1,
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MX3_NF_DATAOUT_NANDID = 2,
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MX3_NF_DATAOUT_NANDSTATUS = 4,
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};
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enum mx_nf_finalize_action {
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MX3_NF_FIN_NONE,
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MX3_NF_FIN_DATAOUT,
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};
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struct mx3_nf_flags {
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unsigned int target_little_endian:1;
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unsigned int nand_readonly:1;
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unsigned int one_kb_sram:1;
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unsigned int hw_ecc_enabled:1;
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};
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struct mx3_nf_controller {
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enum mx_dataout_type optype;
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enum mx_nf_finalize_action fin;
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struct mx3_nf_flags flags;
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};
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#endif /* OPENOCD_FLASH_NAND_MX3_H */
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