* `int riscv_reg_get()` and `int riscv_reg_set()` are implemented in
terms of `reg->type->get/set` instead of the other way around. This
makes it easier to support custom behavior for some registers.
* Cacheability is determined by `reg->type` instead of
`riscv_reg_impl_gdb_regno_cacheable()`.
* Issues with redirection of `priv` -> `dcsr` and `pc` -> `dpc` are
addressed at the "topmost" level.
- `priv` and `pc` are alvais invalid.
- Fixed some issues, e.g. the first `pc` write printed-out an
uninitialized value:
```
> reg pc 0
pc (/64): 0x000075da6b33db20
```
Change-Id: I514547f455d62b289fb5dee62753bf5d9aa3b8ae
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
a54d86f3d0