113 lines
3.3 KiB
ArmAsm
113 lines
3.3 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2015 by Bogdan Kolbov *
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* kolbov@niiet.ru *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc. *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m4
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.thumb
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.thumb_func
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/* K1921VK01T has 128-bitwidth flash, so it`s able to load 4x32-bit words at the time.
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* And only after all words loaded we can start write
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*/
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/* Registers addresses */
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#define FLASH_FMA 0x00 /* Address reg */
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#define FLASH_FMD1 0x04 /* Data1 reg */
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#define FLASH_FMC 0x08 /* Command reg */
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#define FLASH_FCIS 0x0C /* Operation Status reg */
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#define FLASH_FCIC 0x14 /* Operation Status Clear reg */
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#define FLASH_FMD2 0x50 /* Data2 reg */
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#define FLASH_FMD3 0x54 /* Data3 reg */
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#define FLASH_FMD4 0x58 /* Data4 reg*/
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/* Params:
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* r0 - write cmd (in), status (out)
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* r1 - count
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* r2 - workarea start
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* r3 - workarea end
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* r4 - target address
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* Clobbered:
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* r5 - rp
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* r6 - wp, tmp
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* r7 - flash base
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*/
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ldr r7, =#0xA001C000 /* Flash reg base*/
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wait_fifo:
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ldr r6, [r2, #0] /* read wp */
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cmp r6, #0 /* abort if wp == 0 */
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beq exit
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ldr r5, [r2, #4] /* read rp */
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cmp r5, r6 /* wait until rp != wp */
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beq wait_fifo
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load_data:
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ldr r6, [r5] /* read data1 */
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str r6, [r7, #FLASH_FMD1]
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adds r5, #4
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ldr r6, [r5] /* read data2 */
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str r6, [r7, #FLASH_FMD2]
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adds r5, #4
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ldr r6, [r5] /* read data3 */
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str r6, [r7, #FLASH_FMD3]
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adds r5, #4
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ldr r6, [r5] /* read data4 */
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str r6, [r7, #FLASH_FMD4]
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adds r5, #4
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start_write:
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str r4, [r7, #FLASH_FMA] /* set addr */
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adds r4, #16
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str r0, [r7, #FLASH_FMC] /* write cmd */
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busy:
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ldr r6, [r7, #FLASH_FCIS] /* wait until flag set */
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cmp r6, #0x0
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beq busy
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cmp r6, #2 /* check the error bit */
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beq error
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movs r6, #1 /* clear flags */
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str r6, [r7, #FLASH_FCIC]
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cmp r5, r3 /* wrap rp at end of buffer */
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bcc no_wrap
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mov r5, r2
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adds r5, #8
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no_wrap:
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str r5, [r2, #4] /* store rp */
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subs r1, r1, #1 /* decrement 16-byte block count */
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cmp r1, #0
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beq exit /* loop if not done */
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b wait_fifo
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error:
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movs r0, #0
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str r0, [r2, #4] /* set rp = 0 on error */
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exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0
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