da6c0e45a2
We want to keep the tri-state buffers located between the FPGA and the board, in 'Z' state until we launch an i2c connection. We launch an i2c start condition, make the SCL direction 'OUT' to start the i2c protocol and at the end of the i2c connection at the stop condition, we re-make the tri-state buffers at 'Z' state. Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64 Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7989 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> |
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| .. | ||
| buildroot | ||
| firmware/angie | ||
| libdcc | ||
| loaders | ||
| remote_bitbang | ||
| rpc_examples | ||
| rtos-helpers | ||
| xsvf_tools | ||
| 60-openocd.rules | ||
| coresight-trace.txt | ||
| cross-build.sh | ||
| gen-stellaris-part-header.pl | ||
| itmdump.c | ||
| list_example.c | ||