riscv-openocd

History

Tim Newsome bb03f79bde Improve block read and checksum speed (#381 ) * Cache program buffer writes. Speeds up flash program by 3%, flash verify by 2%. Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a * Remove nop from batch reads. program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287 KiB/s, verify @ 23.148 KiB/s originally). Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935 * Use "algorithm" to compute CRC on RISC-V targets. Use the C compiler to generate the algorithm code. It's better at assembly than I am. We need separate RV32 and RV64 binaries to handle shift instructions. I used the code from gdb (libiberty really) because it returns the correct result. I'm not sure if the table is worth it since we do have to save/download/restore more bytes now. riscv_run_algorithm() now properly saves and reads back all registers used for parameters. It also doesn't check final_pc if exit_point is 0. Using gdb means I don't know the exact address where the code will end. Small target.[ch] change to be able to run algorithms at 64-bit addresses. Flashing an arty board now: ``` wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s) verified 2192012 bytes in 7.037476s (304.177 KiB/s) 9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k ``` Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190 * Clean up formatting. Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025		2019-06-19 10:56:37 -07:00
..
checksum	Improve block read and checksum speed (#381 )	2019-06-19 10:56:37 -07:00
debug/xscale	xscale: Move debug handler to contrib/loaders	2016-12-08 13:11:42 +00:00
erase_check	Remove FSF address to satisfy checkpatch	2018-05-14 12:26:04 -07:00
flash	Merge branch 'master' into from_upstream	2019-02-08 14:39:47 -08:00
watchdog	flash Kinetis: handle all types of watchdog, disable in reset-init	2017-06-17 12:01:55 +01:00
Makefile	From upstream (#331 )	2018-11-19 12:46:40 -08:00
README	cortex_m: target implementation renames cortex_m3 to cortex_m	2013-10-10 20:51:03 +00:00

README

Included in these directories are the src to the various ram loaders used
within openocd.

** target checksum loaders **

checksum/armv4_5_crc.s :
 - ARMv4 and ARMv5 checksum loader : see target/arm_crc_code.c:arm_crc_code

checksum/armv7m_crc.s :
 - ARMv7m checksum loader : see target/armv7m.c:cortex_m_crc_code

checksum/mips32.s :
 - MIPS32 checksum loader : see target/mips32.c:mips_crc_code

** target flash loaders **

flash/pic32mx.s :
 - Microchip PIC32 flash loader : see flash/nor/pic32mx.c:pic32mx_flash_write_code

flash/stellaris.s :
 - TI Stellaris flash loader : see flash/nor/stellaris.c:stellaris_write_code

flash/stm32x.s :
 - ST STM32 flash loader : see flash/nor/stm32x.c:stm32x_flash_write_code

flash/str7x.s :
 - ST STR7 flash loader : see flash/nor/str7x.c:str7x_flash_write_code

flash/str9x.s :
 - ST STR9 flash loader : see flash/nor/str9x.c:str9x_flash_write_code

Spencer Oliver
spen@spen-soft.co.uk