riscv-openocd/tcl/target/stm32u5x.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

# script for stm32u5x family

#
# stm32u5 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME stm32u5x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 64kB
if { [info exists WORKAREASIZE] } {
	set _WORKAREASIZE $WORKAREASIZE
} else {
	set _WORKAREASIZE 0x10000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	if { [using_jtag] } {
		# See STM Document RM0438
		# RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
		# Corresponds to Cortex®-M33 JTAG debug port ID code
		set _CPUTAPID 0x0ba04477
	} {
		# SWD IDCODE (single drop, arm)
		set _CPUTAPID 0x0be12477
	}
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

if {[using_jtag]} {
	jtag newtap $_CHIPNAME bs -irlen 5
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

# use non-secure RAM by default
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

# create sec/ns flash and otp memories (sizes will be probed)
flash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME

# Common knowledges tells JTAG speed should be <= F_CPU/6.
# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
# the safe side.
#
# Note that there is a pretty wide band where things are
# more or less stable, see http://openocd.zylin.com/#/c/3366/
adapter speed 500

adapter srst delay 100
if {[using_jtag]} {
	jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
	# if srst is not fitted use SYSRESETREQ to
	# perform a soft reset
	cortex_m reset_config sysresetreq
}

proc is_secure {} {
	# read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
	set DSCSR [mrw 0xE000EE08]
	return [expr {($DSCSR & (1 << 16)) != 0}]
}

proc clock_config_160_mhz {} {
	set offset [expr {[is_secure] ? 0x10000000 : 0}]
	# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL

	# Enable voltage range 1 for frequency above 100 Mhz
	# RCC_AHB3ENR = PWREN
	mww [expr {0x46020C94 + $offset}] 0x00000004
	# delay for register clock enable (read back reg)
	mrw [expr {0x56020C94 + $offset}]
	# PWR_VOSR : VOS Range 1
	mww [expr {0x4602080C + $offset}] 0x00030000
	# delay for register write (read back reg)
	mrw [expr {0x4602080C + $offset}]
	# FLASH_ACR : 4 WS for 160 MHz HCLK
	mww [expr {0x40022000 + $offset}] 0x00000004
	# RCC_PLL1CFGR => PLL1M=0000=/1, PLL1SRC=MSI 4MHz
	mww [expr {0x46020C28 + $offset}] 0x00000001
	# RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
	# fVCO = 4 x 80 /1 = 320
	# SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
	mmw [expr {0x46020C34 + $offset}] 0x0000004F 0
	# RCC_PLL1CFGR => PLL1REN=1
	mmw [expr {0x46020C28 + $offset}] 0x00040000 0
	# RCC_CR |= PLL1ON
	mmw [expr {0x46020C00 + $offset}] 0x01000000 0
	# while !(RCC_CR & PLL1RDY)
	while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}
	# RCC_CFGR1 |= SW_PLL
	mmw [expr {0x46020C1C + $offset}] 0x00000003 0
	# while ((RCC_CFGR1 & SWS) != PLL)
	while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
}

proc ahb_ap_non_secure_access {} {
	# SPROT=1=Non Secure access, Priv=1
	[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
}

proc ahb_ap_secure_access {} {
	# SPROT=0=Secure access, Priv=1
	[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
}

$_TARGETNAME configure -event reset-init {
	clock_config_160_mhz
	# Boost JTAG frequency
	adapter speed 4000
}

$_TARGETNAME configure -event reset-start {
	# Reset clock is MSI (4 MHz)
	adapter speed 480
}

$_TARGETNAME configure -event examine-end {
	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
	mmw 0xE0044004 0x00000006 0

	# Stop watchdog counters during halt
	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
	mmw 0xE0044008 0x00001800 0
}

$_TARGETNAME configure -event halted {
	set secure [is_secure]

	if {$secure} {
		set secure_str "Secure"
		ahb_ap_secure_access
	} else {
		set secure_str "Non-Secure"
		ahb_ap_non_secure_access
	}

	# print the secure state only when it changes
	set _TARGETNAME [target current]
	global $_TARGETNAME.secure

	if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
		echo "CPU in $secure_str state"
		# update saved security state
		set $_TARGETNAME.secure $secure
	}
}

$_TARGETNAME configure -event gdb-flash-erase-start {
	set use_secure_workarea 0
	# check if FLASH_OPTR.TZEN is enabled
	set FLASH_OPTR [mrw 0x40022040]
	if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
		echo "TZEN option bit disabled"
		ahb_ap_non_secure_access
	} else {
		ahb_ap_secure_access
		echo "TZEN option bit enabled"

		# check if FLASH_OPTR.RDP is not Level 0.5
		if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
			set use_secure_workarea 1
		}
	}

	set _TARGETNAME [target current]
	set workarea_addr [$_TARGETNAME cget -work-area-phys]
	echo "workarea_addr $workarea_addr"

	if {$use_secure_workarea} {
		set workarea_addr [expr {$workarea_addr | 0x10000000}]
	} else {
		set workarea_addr [expr {$workarea_addr & ~0x10000000}]
	}

	$_TARGETNAME configure -work-area-phys $workarea_addr
}

$_TARGETNAME configure -event trace-config {
	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
	# change this value accordingly to configure trace pins
	# assignment
	mmw 0xE0044004 0x00000020 0
}