riscv-openocd/src/target/riscv
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
..
Makefile.am openocd: build: add SPDX tag 2022-07-23 13:06:38 +00:00
asm.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
batch.c target/riscv: add dm layer 2023-07-26 01:06:38 +08:00
batch.h target/riscv: add dm layer 2023-07-26 01:06:38 +08:00
debug_defines.h target/riscv: Update debug_defines.h. 2022-08-15 13:18:16 +00:00
encoding.h Update encoding.h. 2023-03-16 11:27:06 -07:00
gdb_regs.h target/riscv: Add constants for vsatp, hgatp 2023-04-25 09:30:27 -07:00
opcodes.h Fix opcode for the "fence" instruction 2023-02-01 14:59:33 +01:00
program.c target/riscv: refactor read_memory_progbuf() 2023-07-14 22:23:02 +03:00
program.h target/riscv: refactor read_memory_progbuf() 2023-07-14 22:23:02 +03:00
riscv-011.c target/riscv: use `riscv_reg_t` and `enum gbb_regno` consistently 2023-05-22 11:55:37 +03:00
riscv-013.c target/riscv: add dm layer 2023-07-26 01:06:38 +08:00
riscv.c target/riscv: add dm layer 2023-07-26 01:06:38 +08:00
riscv.h target/riscv: add dm layer 2023-07-26 01:06:38 +08:00
riscv_semihosting.c target/riscv: Add target logging to most logging instances 2023-07-24 08:03:32 +02:00