riscv-openocd/src
Oleksij Rempel 16e95146be mips_m4k: add optional reset handler
In some cases by using SRST we can't halt CPU early enough. And
option PrRst is not available too. In this case the only way is
to set BOOT flag over EJTAG and reset CPU or SoC from CPU itself.
For example by writing to some reset register.

This patch is providing possibility to use user defined reset-assert
handler which will be enabled only in case SRST is disabled. It is
needed to be able switch between two different reset variants on run
time.

Change-Id: I6ef98f1871ea657115877190f7cc7a5e8f3233e4
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4404
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-07-31 15:54:28 +01:00
..
flash nrf5: Add HWID 0x139 (52832 rev E0) 2018-07-18 21:11:12 +01:00
helper Add RISC-V support. 2018-07-24 13:07:26 +01:00
jtag drivers: cmsis-dap: print serial if available 2018-07-25 14:17:00 +01:00
pld Convert to non-recursive make 2016-12-08 16:23:10 +00:00
rtos ChibiOS thread states: Update thread state to label mapping 2018-04-23 20:46:52 +01:00
server server: Improve signal handling under Linux 2018-07-21 07:43:23 +01:00
svf svf: improve robustness when processing invalid SVF files 2018-03-13 08:41:21 +00:00
target mips_m4k: add optional reset handler 2018-07-31 15:54:28 +01:00
transport configure: disable all drivers when zy1000 is enabled 2018-04-09 09:04:46 +01:00
xsvf Convert to non-recursive make 2016-12-08 16:23:10 +00:00
Makefile.am Convert to non-recursive make 2016-12-08 16:23:10 +00:00
hello.c Remove FSF address from GPL notices 2016-05-24 22:30:01 +01:00
hello.h Make #include guard naming consistent 2016-05-24 22:30:55 +01:00
main.c Remove FSF address from GPL notices 2016-05-24 22:30:01 +01:00
openocd.c armv8: valgrind memleak fixes 2018-04-10 09:13:02 +01:00
openocd.h Make #include guard naming consistent 2016-05-24 22:30:55 +01:00