678fb4f60b
STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4 The second core creation is only done when * DUAL_CORE variable is set to true * non HLA interface is used A second check for the second core existence is done in cpu1 examine-end Once the second core is detected it gets examined. Furthermore, the script provides a configurable CTI usage in order to halt the cores simultaneously. Tested on Rev X and V devices. PS: the indentation was a mix of spaces and tabs, all changed to tabs. Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5130 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> |
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| .. | ||
| at91sam7x | ||
| bluenrg-x | ||
| cc26xx | ||
| cc3220sf | ||
| fespi | ||
| fm4 | ||
| fpga | ||
| kinetis | ||
| kinetis_ke | ||
| max32xxx | ||
| msp432 | ||
| stm32 | ||
| xmc1xxx | ||
| armv4_5_cfi_intel_8.s | ||
| armv4_5_cfi_intel_16.s | ||
| armv4_5_cfi_intel_32.s | ||
| armv4_5_cfi_span_8.s | ||
| armv4_5_cfi_span_16.s | ||
| armv4_5_cfi_span_16_dq7.s | ||
| armv4_5_cfi_span_32.s | ||
| armv7m_cfi_span_16.s | ||
| armv7m_cfi_span_16_dq7.s | ||
| armv7m_io.s | ||
| cortex-m0.S | ||
| efm32.S | ||
| k1921vk01t.S | ||
| lpcspifi_erase.S | ||
| lpcspifi_init.S | ||
| lpcspifi_write.S | ||
| mdr32fx.S | ||
| mrvlqspi_write.S | ||
| pic32mx.s | ||
| sim3x.s | ||
| stellaris.s | ||
| str7x.s | ||
| str9x.s | ||