Tomas Vanek 7e9e5dca07 target/riscv: drop unused variable registers_initialized ... Change-Id: If7bfe38ac273ce9e54003e003807e128cced1568 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6995 Tested-by: jenkins Reviewed-by: Tim Newsome <tim@sifive.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>		2022-06-04 08:20:09 +00:00
..
Makefile.am	Add RISC-V support.	2018-07-24 13:07:26 +01:00
asm.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
batch.c	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
batch.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
debug_defines.h	riscv: Regenerated debug_defines.h and encoding.h	2021-11-20 14:39:13 +00:00
encoding.h	riscv: Regenerated debug_defines.h and encoding.h	2021-11-20 14:39:13 +00:00
gdb_regs.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
opcodes.h	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
program.c	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
program.h	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
riscv-011.c	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
riscv-013.c	target/riscv: fix 'reset run' after 'reset halt'	2022-05-18 09:03:41 +00:00
riscv.c	target/riscv: drop unused variable registers_initialized	2022-06-04 08:20:09 +00:00
riscv.h	target/riscv: drop unused variable registers_initialized	2022-06-04 08:20:09 +00:00
riscv_semihosting.c	semihosting: User defined operation, Tcl command exec on host	2022-02-05 21:40:17 +00:00