165 lines
3.8 KiB
INI
165 lines
3.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
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# Ampere Altra Max ("Mystique") processors
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#
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# Copyright (c) 2019-2021, Ampere Computing LLC
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# Argument Description
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#
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# JTAGFREQ
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# Set the JTAG clock frequency
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# Syntax: -c "set JTAGFREQ {freq_in_khz}"
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#
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# SYSNAME
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# Set the system name
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# If not specified, defaults to "qs"
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# Syntax: -c "set SYSNAME {qs}"
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#
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# Life-Cycle State (LCS)
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# If not specified, defaults to "Secure LCS"
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# LCS=0, "Secure LCS"
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# LCS=1, "Chip Manufacturing LCS"
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# Syntax: -c "set LCS {0}"
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# Syntax: -c "set LCS {1}"
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#
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# CORELIST_S0, CORELIST_S1
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# Specify available physical cores by number
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# Example syntax to connect to physical cores 16 and 17 for S0 and S1
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# Syntax: -c "set CORELIST_S0 {16 17}"
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# Syntax: -c "set CORELIST_S1 {16 17}"
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#
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# COREMASK_S0_LO, COREMASK_S1_LO
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# Specify available physical cores 0-63 by mask
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# Example syntax to connect to physical cores 16 and 17 for S0 and S1
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# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
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# Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}"
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#
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# COREMASK_S0_HI, COREMASK_S1_HI
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# Specify available physical cores 64 and above by mask
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# Example syntax to connect to physical cores 94 and 95 for S0 and S1
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# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
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# Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}"
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#
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# SPLITSMP
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# Group all ARMv8 cores per socket into individual SMP sessions
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# If not specified, group ARMv8 cores from both sockets into one SMP session
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# Syntax: -c "set SPLITSMP {}"
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#
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# PHYS_IDX
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# Enable OpenOCD ARMv8 core target physical indexing
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# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
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# Syntax: -c "set PHYS_IDX {}"
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#
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# Configure JTAG speed
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#
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if { [info exists JTAGFREQ] } {
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adapter speed $JTAGFREQ
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} else {
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adapter speed 100
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}
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#
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# Set the system name
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#
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if { [info exists SYSNAME] } {
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set _SYSNAME $SYSNAME
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} else {
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set _SYSNAME qs
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}
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#
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# Configure Board level SMP configuration if necessary
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#
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if { ![info exists SPLITSMP] } {
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# Group dual chip into a single SMP configuration
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set SMP_STR "target smp"
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set CORE_INDEX_OFFSET 0
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set DUAL_SOCKET_SMP_ENABLED ""
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}
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#
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# Configure Resets
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#
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jtag_ntrst_delay 100
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reset_config trst_only
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#
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# Configure Targets
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#
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if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \
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[info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {
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set CHIPNAME ${_SYSNAME}1
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if { [info exists CORELIST_S1] } {
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set CORELIST $CORELIST_S1
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} else {
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if { [info exists COREMASK_S1_LO] } {
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set COREMASK_LO $COREMASK_S1_LO
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} else {
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set COREMASK_LO 0x0
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}
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if { [info exists COREMASK_S1_HI] } {
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set COREMASK_HI $COREMASK_S1_HI
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} else {
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set COREMASK_HI 0x0
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}
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}
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source [find target/ampere_qs_mq.cfg]
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if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
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if { [info exists MQ_ENABLE] } {
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set CORE_INDEX_OFFSET 128
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} else {
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set CORE_INDEX_OFFSET 80
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}
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}
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set CHIPNAME ${_SYSNAME}0
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if { [info exists CORELIST_S0] } {
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set CORELIST $CORELIST_S0
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} else {
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if { [info exists COREMASK_S0_LO] } {
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set COREMASK_LO $COREMASK_S0_LO
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} else {
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set COREMASK_LO 0x0
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}
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if { [info exists COREMASK_S0_HI] } {
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set COREMASK_HI $COREMASK_S0_HI
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} else {
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set COREMASK_HI 0x0
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}
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}
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source [find target/ampere_qs_mq.cfg]
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} else {
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set CHIPNAME ${_SYSNAME}1
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set COREMASK_LO 0x0
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set COREMASK_HI 0x0
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source [find target/ampere_qs_mq.cfg]
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if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
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if { [info exists MQ_ENABLE] } {
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set CORE_INDEX_OFFSET 128
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} else {
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set CORE_INDEX_OFFSET 80
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}
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}
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set CHIPNAME ${_SYSNAME}0
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set COREMASK_LO 0x1
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set COREMASK_HI 0x0
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source [find target/ampere_qs_mq.cfg]
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}
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if { [info exists DUAL_SOCKET_SMP_ENABLED] } {
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# For dual socket SMP configuration, evaluate the string
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eval $SMP_STR
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}
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