64 lines
2.4 KiB
INI
64 lines
2.4 KiB
INI
################################################################################
|
|
# Atmel AT91SAM9263-EK eval board
|
|
################################################################################
|
|
|
|
source [find mem_helper.tcl]
|
|
source [find target/at91sam9263.cfg]
|
|
uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
|
|
uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
|
|
uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
|
|
uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
|
|
|
|
# By default S1 is open and this means that NTRST is not connected.
|
|
# The reset_config in target/at91sam9263.cfg is overridden here.
|
|
# (or S1 must be populated with a 0 Ohm resistor)
|
|
reset_config srst_only
|
|
|
|
scan_chain
|
|
$_TARGETNAME configure -event gdb-attach { reset init }
|
|
$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
|
|
$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
|
|
|
|
proc at91sam9263ek_reset_init { } {
|
|
|
|
set config(master_pll_div) 14
|
|
set config(master_pll_mul) 171
|
|
|
|
set val [expr $::AT91_WDT_WDV] ;# Counter Value
|
|
set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable
|
|
set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value
|
|
set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt
|
|
set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt
|
|
|
|
set config(wdt_mr_val) $val
|
|
|
|
set config(sdram_piod) 1
|
|
;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
|
|
set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA
|
|
|
|
set val [expr $::AT91_MATRIX_EBI0_DBPUC]
|
|
set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
|
|
set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
|
|
set config(matrix_ebicsa_val) $val
|
|
|
|
;# SDRAMC_CR - Configuration register
|
|
set val [expr $::AT91_SDRAMC_NC_9]
|
|
set val [expr ($val | $::AT91_SDRAMC_NR_13)]
|
|
set val [expr ($val | $::AT91_SDRAMC_NB_4)]
|
|
set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
|
|
set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
|
|
set val [expr ($val | (1 << 8))] ;# Write Recovery Delay
|
|
set val [expr ($val | (7 << 12))] ;# Row Cycle Delay
|
|
set val [expr ($val | (2 << 16))] ;# Row Precharge Delay
|
|
set val [expr ($val | (2 << 20))] ;# Row to Column Delay
|
|
set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay
|
|
set val [expr ($val | (1 << 28))] ;# Exit Self Refresh to Active Delay
|
|
|
|
set config(sdram_cr_val) $val
|
|
|
|
set config(sdram_tr_val) 0x13c
|
|
|
|
set config(sdram_base) $::AT91_CHIPSELECT_1
|
|
at91sam9_reset_init $config
|
|
}
|