500 lines
15 KiB
C
500 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* ESP32 target API for OpenOCD *
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* Copyright (C) 2016-2019 Espressif Systems Ltd. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/time_support.h>
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#include <target/target.h>
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#include <target/target_type.h>
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#include <target/smp.h>
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#include <target/semihosting_common.h>
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#include "assert.h"
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#include "esp_xtensa_smp.h"
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/*
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This is a JTAG driver for the ESP32, the are two Tensilica cores inside
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the ESP32 chip. For more information please have a look into ESP32 target
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implementation.
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*/
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/* ESP32 memory map */
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#define ESP32_RTC_DATA_LOW 0x50000000
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#define ESP32_RTC_DATA_HIGH 0x50002000
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#define ESP32_DR_REG_LOW 0x3ff00000
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#define ESP32_DR_REG_HIGH 0x3ff71000
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#define ESP32_SYS_RAM_LOW 0x60000000UL
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#define ESP32_SYS_RAM_HIGH (ESP32_SYS_RAM_LOW + 0x20000000UL)
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#define ESP32_RTC_SLOW_MEM_BASE ESP32_RTC_DATA_LOW
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/* ESP32 WDT */
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#define ESP32_WDT_WKEY_VALUE 0x50d83aa1
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#define ESP32_TIMG0_BASE 0x3ff5f000
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#define ESP32_TIMG1_BASE 0x3ff60000
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#define ESP32_TIMGWDT_CFG0_OFF 0x48
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#define ESP32_TIMGWDT_PROTECT_OFF 0x64
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#define ESP32_TIMG0WDT_CFG0 (ESP32_TIMG0_BASE + ESP32_TIMGWDT_CFG0_OFF)
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#define ESP32_TIMG1WDT_CFG0 (ESP32_TIMG1_BASE + ESP32_TIMGWDT_CFG0_OFF)
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#define ESP32_TIMG0WDT_PROTECT (ESP32_TIMG0_BASE + ESP32_TIMGWDT_PROTECT_OFF)
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#define ESP32_TIMG1WDT_PROTECT (ESP32_TIMG1_BASE + ESP32_TIMGWDT_PROTECT_OFF)
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#define ESP32_RTCCNTL_BASE 0x3ff48000
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#define ESP32_RTCWDT_CFG_OFF 0x8C
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#define ESP32_RTCWDT_PROTECT_OFF 0xA4
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#define ESP32_RTCWDT_CFG (ESP32_RTCCNTL_BASE + ESP32_RTCWDT_CFG_OFF)
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#define ESP32_RTCWDT_PROTECT (ESP32_RTCCNTL_BASE + ESP32_RTCWDT_PROTECT_OFF)
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#define ESP32_TRACEMEM_BLOCK_SZ 0x4000
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/* ESP32 dport regs */
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#define ESP32_DR_REG_DPORT_BASE ESP32_DR_REG_LOW
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#define ESP32_DPORT_APPCPU_CTRL_B_REG (ESP32_DR_REG_DPORT_BASE + 0x030)
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#define ESP32_DPORT_APPCPU_CLKGATE_EN BIT(0)
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/* ESP32 RTC regs */
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#define ESP32_RTC_CNTL_SW_CPU_STALL_REG (ESP32_RTCCNTL_BASE + 0xac)
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#define ESP32_RTC_CNTL_SW_CPU_STALL_DEF 0x0
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/* 0 - don't care, 1 - TMS low, 2 - TMS high */
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enum esp32_flash_bootstrap {
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FBS_DONTCARE = 0,
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FBS_TMSLOW,
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FBS_TMSHIGH,
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};
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struct esp32_common {
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struct esp_xtensa_smp_common esp_xtensa_smp;
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enum esp32_flash_bootstrap flash_bootstrap;
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};
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static inline struct esp32_common *target_to_esp32(struct target *target)
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{
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return container_of(target->arch_info, struct esp32_common, esp_xtensa_smp);
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}
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/* Reset ESP32 peripherals.
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* Postconditions: all peripherals except RTC_CNTL are reset, CPU's PC is undefined, PRO CPU is halted,
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* APP CPU is in reset
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* How this works:
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* 0. make sure target is halted; if not, try to halt it; if that fails, try to reset it (via OCD) and then halt
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* 1. set CPU initial PC to 0x50000000 (ESP32_SMP_RTC_DATA_LOW) by clearing RTC_CNTL_{PRO,APP}CPU_STAT_VECTOR_SEL
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* 2. load stub code into ESP32_SMP_RTC_DATA_LOW; once executed, stub code will disable watchdogs and
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* make CPU spin in an idle loop.
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* 3. trigger SoC reset using RTC_CNTL_SW_SYS_RST bit
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* 4. wait for the OCD to be reset
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* 5. halt the target and wait for it to be halted (at this point CPU is in the idle loop)
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* 6. restore initial PC and the contents of ESP32_SMP_RTC_DATA_LOW
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* TODO: some state of RTC_CNTL is not reset during SW_SYS_RST. Need to reset that manually. */
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static const uint8_t esp32_reset_stub_code[] = {
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#include "../../../contrib/loaders/reset/espressif/esp32/cpu_reset_handler_code.inc"
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};
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static int esp32_soc_reset(struct target *target)
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{
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int res;
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struct target_list *head;
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struct xtensa *xtensa;
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LOG_DEBUG("start");
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/* In order to write to peripheral registers, target must be halted first */
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if (target->state != TARGET_HALTED) {
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LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
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xtensa_halt(target);
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res = target_wait_state(target, TARGET_HALTED, 1000);
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if (res != ERROR_OK) {
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LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
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res = xtensa_assert_reset(target);
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if (res != ERROR_OK) {
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LOG_ERROR(
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"Couldn't halt target before SoC reset! (xtensa_assert_reset returned %d)",
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res);
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return res;
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}
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alive_sleep(10);
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xtensa_poll(target);
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bool reset_halt_save = target->reset_halt;
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target->reset_halt = true;
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res = xtensa_deassert_reset(target);
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target->reset_halt = reset_halt_save;
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if (res != ERROR_OK) {
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LOG_ERROR(
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"Couldn't halt target before SoC reset! (xtensa_deassert_reset returned %d)",
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res);
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return res;
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}
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alive_sleep(10);
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xtensa_poll(target);
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xtensa_halt(target);
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res = target_wait_state(target, TARGET_HALTED, 1000);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't halt target before SoC reset");
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return res;
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}
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}
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}
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if (target->smp) {
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foreach_smp_target(head, target->smp_targets) {
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xtensa = target_to_xtensa(head->target);
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/* if any of the cores is stalled unstall them */
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if (xtensa_dm_core_is_stalled(&xtensa->dbg_mod)) {
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LOG_TARGET_DEBUG(head->target, "Unstall CPUs before SW reset!");
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res = target_write_u32(target,
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ESP32_RTC_CNTL_SW_CPU_STALL_REG,
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ESP32_RTC_CNTL_SW_CPU_STALL_DEF);
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if (res != ERROR_OK) {
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LOG_TARGET_ERROR(head->target, "Failed to unstall CPUs before SW reset!");
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return res;
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}
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break; /* both cores are unstalled now, so exit the loop */
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}
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}
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}
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LOG_DEBUG("Loading stub code into RTC RAM");
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uint8_t slow_mem_save[sizeof(esp32_reset_stub_code)];
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/* Save contents of RTC_SLOW_MEM which we are about to overwrite */
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res = target_read_buffer(target, ESP32_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to save contents of RTC_SLOW_MEM (%d)!", res);
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return res;
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}
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/* Write stub code into RTC_SLOW_MEM */
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res = target_write_buffer(target, ESP32_RTC_SLOW_MEM_BASE, sizeof(esp32_reset_stub_code), esp32_reset_stub_code);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write stub (%d)!", res);
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return res;
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}
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LOG_DEBUG("Resuming the target");
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xtensa = target_to_xtensa(target);
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xtensa->suppress_dsr_errors = true;
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res = xtensa_resume(target, 0, ESP32_RTC_SLOW_MEM_BASE + 4, 0, 0);
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xtensa->suppress_dsr_errors = false;
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to run stub (%d)!", res);
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return res;
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}
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LOG_DEBUG("resume done, waiting for the target to come alive");
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/* Wait for SoC to reset */
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alive_sleep(100);
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int64_t timeout = timeval_ms() + 100;
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bool get_timeout = false;
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while (target->state != TARGET_RESET && target->state != TARGET_RUNNING) {
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alive_sleep(10);
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xtensa_poll(target);
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if (timeval_ms() >= timeout) {
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LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
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target->state);
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get_timeout = true;
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break;
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}
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}
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/* Halt the CPU again */
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LOG_DEBUG("halting the target");
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xtensa_halt(target);
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res = target_wait_state(target, TARGET_HALTED, 1000);
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if (res == ERROR_OK) {
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LOG_DEBUG("restoring RTC_SLOW_MEM");
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res = target_write_buffer(target, ESP32_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
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if (res != ERROR_OK)
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LOG_TARGET_ERROR(target, "Failed to restore contents of RTC_SLOW_MEM (%d)!", res);
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} else {
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LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be halted after SoC reset");
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}
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return get_timeout ? ERROR_TARGET_TIMEOUT : res;
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}
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static int esp32_disable_wdts(struct target *target)
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{
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/* TIMG1 WDT */
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int res = target_write_u32(target, ESP32_TIMG0WDT_PROTECT, ESP32_WDT_WKEY_VALUE);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_TIMG0WDT_PROTECT (%d)!", res);
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return res;
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}
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res = target_write_u32(target, ESP32_TIMG0WDT_CFG0, 0);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_TIMG0WDT_CFG0 (%d)!", res);
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return res;
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}
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/* TIMG2 WDT */
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res = target_write_u32(target, ESP32_TIMG1WDT_PROTECT, ESP32_WDT_WKEY_VALUE);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_TIMG1WDT_PROTECT (%d)!", res);
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return res;
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}
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res = target_write_u32(target, ESP32_TIMG1WDT_CFG0, 0);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_TIMG1WDT_CFG0 (%d)!", res);
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return res;
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}
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/* RTC WDT */
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res = target_write_u32(target, ESP32_RTCWDT_PROTECT, ESP32_WDT_WKEY_VALUE);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_RTCWDT_PROTECT (%d)!", res);
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return res;
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}
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res = target_write_u32(target, ESP32_RTCWDT_CFG, 0);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_RTCWDT_CFG (%d)!", res);
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return res;
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}
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return ERROR_OK;
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}
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static int esp32_on_halt(struct target *target)
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{
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int ret = esp32_disable_wdts(target);
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if (ret == ERROR_OK)
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ret = esp_xtensa_smp_on_halt(target);
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return ret;
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}
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static int esp32_arch_state(struct target *target)
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{
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return ERROR_OK;
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}
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static int esp32_virt2phys(struct target *target,
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target_addr_t virtual, target_addr_t *physical)
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{
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if (physical) {
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*physical = virtual;
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return ERROR_OK;
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}
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return ERROR_FAIL;
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}
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/* The TDI pin is also used as a flash Vcc bootstrap pin. If we reset the CPU externally, the last state of the TDI pin
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* can allow the power to an 1.8V flash chip to be raised to 3.3V, or the other way around. Users can use the
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* esp32 flashbootstrap command to set a level, and this routine will make sure the tdi line will return to
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* that when the jtag port is idle. */
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static void esp32_queue_tdi_idle(struct target *target)
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{
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struct esp32_common *esp32 = target_to_esp32(target);
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static uint32_t value;
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uint8_t t[4] = { 0, 0, 0, 0 };
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if (esp32->flash_bootstrap == FBS_TMSLOW)
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/* Make sure tdi is 0 at the exit of queue execution */
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value = 0;
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else if (esp32->flash_bootstrap == FBS_TMSHIGH)
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/* Make sure tdi is 1 at the exit of queue execution */
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value = 1;
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else
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return;
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/* Scan out 1 bit, do not move from IRPAUSE after we're done. */
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buf_set_u32(t, 0, 1, value);
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jtag_add_plain_ir_scan(1, t, NULL, TAP_IRPAUSE);
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}
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static int esp32_target_init(struct command_context *cmd_ctx, struct target *target)
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{
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return esp_xtensa_smp_target_init(cmd_ctx, target);
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}
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static const struct xtensa_debug_ops esp32_dbg_ops = {
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.queue_enable = xtensa_dm_queue_enable,
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.queue_reg_read = xtensa_dm_queue_reg_read,
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.queue_reg_write = xtensa_dm_queue_reg_write
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};
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static const struct xtensa_power_ops esp32_pwr_ops = {
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.queue_reg_read = xtensa_dm_queue_pwr_reg_read,
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.queue_reg_write = xtensa_dm_queue_pwr_reg_write
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};
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static const struct esp_xtensa_smp_chip_ops esp32_chip_ops = {
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.reset = esp32_soc_reset,
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.on_halt = esp32_on_halt
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};
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static const struct esp_semihost_ops esp32_semihost_ops = {
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.prepare = esp32_disable_wdts
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};
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static int esp32_target_create(struct target *target, Jim_Interp *interp)
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{
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struct xtensa_debug_module_config esp32_dm_cfg = {
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.dbg_ops = &esp32_dbg_ops,
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.pwr_ops = &esp32_pwr_ops,
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.tap = target->tap,
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.queue_tdi_idle = esp32_queue_tdi_idle,
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.queue_tdi_idle_arg = target
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};
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struct esp32_common *esp32 = calloc(1, sizeof(struct esp32_common));
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if (!esp32) {
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LOG_ERROR("Failed to alloc memory for arch info!");
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return ERROR_FAIL;
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}
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int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp,
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&esp32_dm_cfg, &esp32_chip_ops, &esp32_semihost_ops);
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if (ret != ERROR_OK) {
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LOG_ERROR("Failed to init arch info!");
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free(esp32);
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return ret;
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}
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esp32->flash_bootstrap = FBS_DONTCARE;
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/* Assume running target. If different, the first poll will fix this. */
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target->state = TARGET_RUNNING;
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target->debug_reason = DBG_REASON_NOTHALTED;
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return ERROR_OK;
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}
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static COMMAND_HELPER(esp32_cmd_flashbootstrap_do, struct esp32_common *esp32)
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{
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int state = -1;
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if (CMD_ARGC < 1) {
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const char *st;
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state = esp32->flash_bootstrap;
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if (state == FBS_DONTCARE)
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st = "Don't care";
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else if (state == FBS_TMSLOW)
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st = "Low (3.3V)";
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else if (state == FBS_TMSHIGH)
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st = "High (1.8V)";
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else
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st = "None";
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command_print(CMD, "Current idle tms state: %s", st);
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return ERROR_OK;
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}
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if (!strcasecmp(CMD_ARGV[0], "none"))
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state = FBS_DONTCARE;
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else if (!strcasecmp(CMD_ARGV[0], "1.8"))
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state = FBS_TMSHIGH;
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else if (!strcasecmp(CMD_ARGV[0], "3.3"))
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state = FBS_TMSLOW;
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else if (!strcasecmp(CMD_ARGV[0], "high"))
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state = FBS_TMSHIGH;
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else if (!strcasecmp(CMD_ARGV[0], "low"))
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state = FBS_TMSLOW;
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if (state == -1) {
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command_print(CMD,
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"Argument unknown. Please pick one of none, high, low, 1.8 or 3.3");
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return ERROR_FAIL;
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}
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esp32->flash_bootstrap = state;
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return ERROR_OK;
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}
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COMMAND_HANDLER(esp32_cmd_flashbootstrap)
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{
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struct target *target = get_current_target(CMD_CTX);
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if (target->smp) {
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struct target_list *head;
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struct target *curr;
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foreach_smp_target(head, target->smp_targets) {
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curr = head->target;
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int ret = CALL_COMMAND_HANDLER(esp32_cmd_flashbootstrap_do,
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target_to_esp32(curr));
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if (ret != ERROR_OK)
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return ret;
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}
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return ERROR_OK;
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}
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return CALL_COMMAND_HANDLER(esp32_cmd_flashbootstrap_do,
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target_to_esp32(target));
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}
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static const struct command_registration esp32_any_command_handlers[] = {
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{
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.name = "flashbootstrap",
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.handler = esp32_cmd_flashbootstrap,
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.mode = COMMAND_ANY,
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.help =
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"Set the idle state of the TMS pin, which at reset also is the voltage selector for the flash chip.",
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.usage = "none|1.8|3.3|high|low",
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},
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COMMAND_REGISTRATION_DONE
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};
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static const struct command_registration esp32_command_handlers[] = {
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{
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.chain = esp_xtensa_smp_command_handlers,
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},
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{
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.name = "esp",
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.usage = "",
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.chain = esp32_apptrace_command_handlers,
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},
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{
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.name = "esp32",
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.usage = "",
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.chain = smp_command_handlers,
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},
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{
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.name = "esp32",
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.usage = "",
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.chain = esp32_any_command_handlers,
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},
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{
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.name = "arm",
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.mode = COMMAND_ANY,
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.help = "ARM Command Group",
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.usage = "",
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.chain = semihosting_common_handlers
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},
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COMMAND_REGISTRATION_DONE
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};
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/** Holds methods for Xtensa targets. */
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struct target_type esp32_target = {
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.name = "esp32",
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.poll = esp_xtensa_smp_poll,
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.arch_state = esp32_arch_state,
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.halt = xtensa_halt,
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.resume = esp_xtensa_smp_resume,
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.step = esp_xtensa_smp_step,
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.assert_reset = esp_xtensa_smp_assert_reset,
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.deassert_reset = esp_xtensa_smp_deassert_reset,
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.soft_reset_halt = esp_xtensa_smp_soft_reset_halt,
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.virt2phys = esp32_virt2phys,
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.mmu = xtensa_mmu_is_enabled,
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.read_memory = xtensa_read_memory,
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.write_memory = xtensa_write_memory,
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.read_buffer = xtensa_read_buffer,
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.write_buffer = xtensa_write_buffer,
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.checksum_memory = xtensa_checksum_memory,
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.get_gdb_arch = xtensa_get_gdb_arch,
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.get_gdb_reg_list = xtensa_get_gdb_reg_list,
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.add_breakpoint = esp_xtensa_breakpoint_add,
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.remove_breakpoint = esp_xtensa_breakpoint_remove,
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.add_watchpoint = esp_xtensa_smp_watchpoint_add,
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.remove_watchpoint = esp_xtensa_smp_watchpoint_remove,
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.target_create = esp32_target_create,
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.init_target = esp32_target_init,
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.examine = xtensa_examine,
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.deinit_target = esp_xtensa_target_deinit,
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.commands = esp32_command_handlers,
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};
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