481 lines
14 KiB
INI
481 lines
14 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
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#
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# Texas Instruments K3 devices:
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# * AM243: https://www.ti.com/lit/pdf/spruim2
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# Has 4 R5 Cores, M4F and an M3
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# * AM263: https://www.ti.com/lit/pdf/spruj17
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# Has 4 R5 Cores and an M3
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# * AM273: https://www.ti.com/lit/pdf/spruiu0
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# Has 2 R5 Cores and an M3
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# * AM625: https://www.ti.com/lit/pdf/spruiv7a
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# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
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# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
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# Has 4 ARMV8 Cores and 2 R5 Cores
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# * AM62P: https://www.ti.com/lit/pdf/spruj83
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# Has 4 ARMV8 Cores and 2 R5 Cores
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# * AM642: https://www.ti.com/lit/pdf/spruim2
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# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
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# * AM654x: https://www.ti.com/lit/pdf/spruid7
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# Has 4 ARMV8 Cores and 2 R5 Cores and an M3
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# * J7200: https://www.ti.com/lit/pdf/spruiu1
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# Has 2 ARMV8 Cores and 4 R5 Cores and an M3
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# * J721E: https://www.ti.com/lit/pdf/spruil1
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# Has 2 ARMV8 Cores and 6 R5 Cores and an M3
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# * J721S2: https://www.ti.com/lit/pdf/spruj28
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# Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
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# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
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# Has 8 ARMV8 Cores and 8 R5 Cores
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#
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source [find target/swj-dp.tcl]
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if { [info exists SOC] } {
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set _soc $SOC
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} else {
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set _soc am654
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}
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# set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
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if { [info exists V8_SMP_DEBUG] } {
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set _v8_smp_debug $V8_SMP_DEBUG
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} else {
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set _v8_smp_debug 0
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}
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# Common Definitions
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# System Controller is the very first processor - all current SoCs have it.
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set CM3_CTIBASE {0x3C016000}
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# sysctrl power-ap unlock offsets
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set _sysctrl_ap_unlock_offsets {0xf0 0x44}
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set _sysctrl_ap_num 7
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# All the ARMV8s are the next processors.
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# CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
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set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
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set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
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# And we add up the R5s
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# (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
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set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
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set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
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set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
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set _r5_ap_num 1
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# Finally an General Purpose(GP) MCU
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set CM4_CTIBASE {0x20001000}
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# General Purpose MCU (M4) may be present on some very few SoCs
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set _gp_mcu_cores 0
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# General Purpose MCU power-ap unlock offsets
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set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
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# Generic mem-ap port number
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set _mem_ap_num 2
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# Set configuration overrides for each SOC
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switch $_soc {
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am263 {
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set _K3_DAP_TAPID 0x2bb7d02f
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# Mem-ap port
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set _mem_ap_num 6
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# AM263 has 0 ARMV8 CPUs
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set _armv8_cores 0
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# AM263 has 2 cluster of 2 R5s cores.
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set _r5_cores 4
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set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
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set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
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set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
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set _r5_ap_num 5
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}
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am273 {
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set _K3_DAP_TAPID 0x1bb6a02f
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# Mem-ap port
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set _mem_ap_num 6
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# system controller is on AP0
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set _sysctrl_ap_num 0
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# AM273 has 0 ARMV8 CPUs
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set _armv8_cores 0
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# AM273 has 1 cluster of 2 R5s cores.
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set _r5_cores 2
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set R5_NAMES {main0_r5.0 main0_r5.1}
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set R5_DBGBASE {0x90030000 0x90032000}
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set R5_CTIBASE {0x90038000 0x90039000}
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set _r5_ap_num 5
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}
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am654 {
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set _K3_DAP_TAPID 0x0bb5a02f
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# AM654 has 2 clusters of 2 A53 cores each.
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set _armv8_cpu_name a53
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set _armv8_cores 4
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# AM654 has 1 cluster of 2 R5s cores.
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set _r5_cores 2
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set R5_NAMES {mcu_r5.0 mcu_r5.1}
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# Sysctrl power-ap unlock offsets
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set _sysctrl_ap_unlock_offsets {0xf0 0x50}
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}
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am243 -
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am642 {
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set _K3_DAP_TAPID 0x0bb3802f
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# AM642 has 1 clusters of 2 A53 cores each.
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set _armv8_cpu_name a53
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set _armv8_cores 2
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set ARMV8_DBGBASE {0x90010000 0x90110000}
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set ARMV8_CTIBASE {0x90020000 0x90120000}
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# AM642 has 2 cluster of 2 R5s cores.
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set _r5_cores 4
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set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
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set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
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set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
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# M4 processor
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set _gp_mcu_cores 1
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# Overrides for am243
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if { "$_soc" == "am243" } {
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# Uses the same JTAG ID
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set _armv8_cores 0
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}
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}
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am625 {
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set _K3_DAP_TAPID 0x0bb7e02f
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# AM625 has 1 clusters of 4 A53 cores.
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set _armv8_cpu_name a53
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set _armv8_cores 4
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set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
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set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
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# AM625 has 1 cluster of 1 R5s core.
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set _r5_cores 1
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set R5_NAMES {main0_r5.0}
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set R5_DBGBASE {0x9d410000}
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set R5_CTIBASE {0x9d418000}
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# sysctrl CTI base
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set CM3_CTIBASE {0x20001000}
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# Sysctrl power-ap unlock offsets
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set _sysctrl_ap_unlock_offsets {0xf0 0x78}
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# M4 processor
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set _gp_mcu_cores 1
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set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
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# Setup DMEM access descriptions
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# DAPBUS (Debugger) description
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set _dmem_base_address 0x740002000
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set _dmem_ap_address_offset 0x100
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set _dmem_max_aps 10
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# Emulated AP description
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set _dmem_emu_base_address 0x760000000
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set _dmem_emu_base_address_map_to 0x1d500000
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set _dmem_emu_ap_list 1
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}
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am62p -
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am62a7 {
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set _K3_DAP_TAPID 0x0bb8d02f
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# AM62a7/AM62P has 1 cluster of 4 A53 cores.
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set _armv8_cpu_name a53
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set _armv8_cores 4
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set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
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set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
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# AM62a7/AM62P has 2 cluster of 1 R5 core.
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set _r5_cores 2
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set R5_NAMES {main0_r5.0 mcu0_r5.0}
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set R5_DBGBASE {0x9d410000 0x9d810000}
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set R5_CTIBASE {0x9d418000 0x9d818000}
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# sysctrl CTI base
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set CM3_CTIBASE {0x20001000}
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# Sysctrl power-ap unlock offsets
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set _sysctrl_ap_unlock_offsets {0xf0 0x78}
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# Overrides for am62p
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if { "$_soc" == "am62p" } {
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set _K3_DAP_TAPID 0x0bb9d02f
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set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
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}
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}
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j721e {
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set _K3_DAP_TAPID 0x0bb6402f
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# J721E has 1 cluster of 2 A72 cores.
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set _armv8_cpu_name a72
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set _armv8_cores 2
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# J721E has 3 clusters of 2 R5 cores each.
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set _r5_cores 6
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# Setup DMEM access descriptions
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# DAPBUS (Debugger) description
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set _dmem_base_address 0x4c40002000
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set _dmem_ap_address_offset 0x100
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set _dmem_max_aps 8
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# Emulated AP description
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set _dmem_emu_base_address 0x4c60000000
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set _dmem_emu_base_address_map_to 0x1d600000
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set _dmem_emu_ap_list 1
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}
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j7200 {
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set _K3_DAP_TAPID 0x0bb6d02f
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# J7200 has 1 cluster of 2 A72 cores.
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set _armv8_cpu_name a72
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set _armv8_cores 2
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# J7200 has 2 clusters of 2 R5 cores each.
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set _r5_cores 4
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set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
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set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
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# M3 CTI base
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set CM3_CTIBASE {0x20001000}
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}
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j721s2 {
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set _K3_DAP_TAPID 0x0bb7502f
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# J721s2 has 1 cluster of 2 A72 cores.
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set _armv8_cpu_name a72
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set _armv8_cores 2
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# J721s2 has 3 clusters of 2 R5 cores each.
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set _r5_cores 6
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# sysctrl CTI base
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set CM3_CTIBASE {0x20001000}
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# Sysctrl power-ap unlock offsets
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set _sysctrl_ap_unlock_offsets {0xf0 0x78}
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# M4 processor
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set _gp_mcu_cores 1
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set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
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}
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j784s4 {
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set _K3_DAP_TAPID 0x0bb8002f
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# j784s4 has 2 cluster of 4 A72 cores each.
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set _armv8_cpu_name a72
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set _armv8_cores 8
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set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
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0x90810000 0x90910000 0x90a10000 0x90b10000}
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set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
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0x90820000 0x90920000 0x90a20000 0x90b20000}
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# J721s2 has 4 clusters of 2 R5 cores each.
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set _r5_cores 8
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set R5_DBGBASE {0x9d010000 0x9d012000
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0x9d410000 0x9d412000
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0x9d510000 0x9d512000
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0x9d610000 0x9d612000}
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set R5_CTIBASE {0x9d018000 0x9d019000
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0x9d418000 0x9d419000
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0x9d518000 0x9d519000
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0x9d618000 0x9d619000}
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set R5_NAMES {mcu_r5.0 mcu_r5.1
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main0_r5.0 main0_r5.1
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main1_r5.0 main1_r5.1
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main2_r5.0 main2_r5.1}
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# sysctrl CTI base
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set CM3_CTIBASE {0x20001000}
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# Sysctrl power-ap unlock offsets
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set _sysctrl_ap_unlock_offsets {0xf0 0x78}
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}
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default {
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echo "'$_soc' is invalid!"
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}
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}
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proc _get_rtos_type_for_cpu { target_name } {
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if { [info exists ::RTOS($target_name)] } {
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return $::RTOS($target_name)
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}
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return none
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}
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set _CHIPNAME $_soc
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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set _CTINAME $_CHIPNAME.cti
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# sysctrl is always present
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cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
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-ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
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target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
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-ap-num $_sysctrl_ap_num -defer-examine \
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-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
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$_TARGETNAME.sysctrl configure -event reset-assert { }
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proc sysctrl_up {} {
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# To access sysctrl, we need to enable the JTAG access for the same.
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# Ensure Power-AP unlocked
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$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
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$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
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$::_TARGETNAME.sysctrl arp_examine
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}
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$_TARGETNAME.sysctrl configure -event gdb-attach {
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sysctrl_up
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# gdb-attach default rule
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halt 1000
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}
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proc _cpu_no_smp_up {} {
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set _current_target [target current]
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set _current_type [$_current_target cget -type]
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$_current_target arp_examine
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$_current_target $_current_type dbginit
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}
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proc _armv8_smp_up {} {
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for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
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$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
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$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
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$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
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}
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# Set Default target as core 0
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targets $::_TARGETNAME.$::_armv8_cpu_name.0
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}
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set _v8_smp_targets ""
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for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
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cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
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-baseaddr [lindex $ARMV8_CTIBASE $_core]
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target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
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-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
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-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
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set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
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if { $_v8_smp_debug == 0 } {
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$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
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_cpu_no_smp_up
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# gdb-attach default rule
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halt 1000
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}
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} else {
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$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
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_armv8_smp_up
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# gdb-attach default rule
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halt 1000
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}
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}
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}
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if { $_armv8_cores > 0 } {
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# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
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set _armv8_up_cmd "$_armv8_cpu_name"_up
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# Available if V8_SMP_DEBUG is set to non-zero value
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set _armv8_smp_cmd "$_armv8_cpu_name"_smp
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if { $_v8_smp_debug == 0 } {
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proc $_armv8_up_cmd { args } {
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foreach _core $args {
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targets $_core
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_cpu_no_smp_up
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}
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}
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} else {
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proc $_armv8_smp_cmd { args } {
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_armv8_smp_up
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}
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# Declare SMP
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target smp {*}$_v8_smp_targets
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}
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}
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for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
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set _r5_name [lindex $R5_NAMES $_core]
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cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
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-baseaddr [lindex $R5_CTIBASE $_core]
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# inactive core examination will fail - wait till startup of additional core
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target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
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-dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
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-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
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$_TARGETNAME.$_r5_name configure -event gdb-attach {
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_cpu_no_smp_up
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# gdb-attach default rule
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halt 1000
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}
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}
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proc r5_up { args } {
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foreach _core $args {
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targets $_core
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_cpu_no_smp_up
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}
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}
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if { $_gp_mcu_cores != 0 } {
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cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
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|
target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
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-rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
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|
$_TARGETNAME.gp_mcu configure -event reset-assert { }
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|
|
|
proc gp_mcu_up {} {
|
|
# To access GP MCU, we need to enable the JTAG access for the same.
|
|
# Ensure Power-AP unlocked
|
|
$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
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|
$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
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|
|
|
$::_TARGETNAME.gp_mcu arp_examine
|
|
}
|
|
|
|
$_TARGETNAME.gp_mcu configure -event gdb-attach {
|
|
gp_mcu_up
|
|
# gdb-attach default rule
|
|
halt 1000
|
|
}
|
|
}
|
|
|
|
# In case of DMEM access, configure the dmem adapter with offsets from above.
|
|
if { 0 == [string compare [adapter name] dmem ] } {
|
|
if { [info exists _dmem_base_address] } {
|
|
# DAPBUS (Debugger) description
|
|
dmem base_address $_dmem_base_address
|
|
dmem ap_address_offset $_dmem_ap_address_offset
|
|
dmem max_aps $_dmem_max_aps
|
|
|
|
# The following are the details of APs to be emulated for direct address access.
|
|
# Debug Config (Debugger) description
|
|
dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
|
|
dmem emu_ap_list $_dmem_emu_ap_list
|
|
# We are going local bus, so speed is really dummy here.
|
|
adapter speed 2500
|
|
} else {
|
|
puts "ERROR: ${SOC} data is missing to support dmem access!"
|
|
}
|
|
} else {
|
|
# AXI AP access port for SoC address map
|
|
target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
|
|
}
|