120 lines
3.8 KiB
INI
120 lines
3.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# GigaDevice GD32VF103 target
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#
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# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
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#
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source [find mem_helper.tcl]
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transport select jtag
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME gd32vf103
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}
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# The smallest RAM size 6kB (GD32VF103C4/T4/R4)
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1800
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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proc default_mem_access {} {
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riscv set_mem_access progbuf
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}
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default_mem_access
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
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# DBGMCU_CR register cannot be set in examine-end event as the running RISC-V CPU
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# does not allow the debugger to access memory.
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# Stop watchdogs at least before flash programming.
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$_TARGETNAME configure -event reset-init {
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# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP
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mmw 0xE0042004 0x00000300 0
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}
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# On this chip, ndmreset (the debug module bit that triggers a software reset)
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# doesn't work. So for JTAG connections without an SRST, we need to trigger a
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# reset manually. This is an undocumented reset sequence that's used by the
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# JTAG flashing script in the vendor-supplied GD32VF103 PlatformIO plugin:
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#
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# https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2
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#
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$_TARGETNAME configure -event reset-assert {
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set dmcontrol 0x10
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set dmcontrol_dmactive [expr {1 << 0}]
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set dmcontrol_ackhavereset [expr {1 << 28}]
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set dmcontrol_haltreq [expr {1 << 31}]
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global _RESETMODE
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# If hardware NRST signal is connected and configured (reset_config srst_only)
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# the device has been recently reset in 'jtag arp_init-reset', therefore
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# DM_DMSTATUS_ANYHAVERESET reads 1.
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# The following 'halt' command checks this status bit
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# and shows 'Hart 0 unexpectedly reset!' if set.
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# Prevent this message by sending an acknowledge first.
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set val [expr {$dmcontrol_dmactive | $dmcontrol_ackhavereset}]
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riscv dmi_write $dmcontrol $val
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# Halt the core so that we can write to memory. We do this first so
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# that it doesn't clobber our dmcontrol configuration.
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halt
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# Set haltreq appropriately for the type of reset we're doing. This
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# replicates what the generic RISC-V reset_assert() function would
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# do if we weren't overriding it. The $_RESETMODE hack sucks, but
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# it's the least invasive way to determine whether we need to halt.
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#
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# If we didn't override the generic handler, we'd actually still have
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# to do this: the default handler sets ndmreset, which prevents memory
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# access even though it doesn't actually trigger a reset on this chip.
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# So we'd need to unset it here, which involves a write to dmcontrol,
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# Since haltreq is write-only and there's no way to leave it unchanged,
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# we'd have to figure out its proper value anyway.
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set val $dmcontrol_dmactive
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if {$_RESETMODE ne "run"} {
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set val [expr {$val | $dmcontrol_haltreq}]
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}
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riscv dmi_write $dmcontrol $val
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# Unlock 0xe0042008 so that the next write triggers a reset
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mww 0xe004200c 0x4b5a6978
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# We need to trigger the reset using abstract memory access, since
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# progbuf access tries to read a status code out of a core register
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# after the write happens, which fails when the core is in reset.
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riscv set_mem_access abstract
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# Go!
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mww 0xe0042008 0x1
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# Put the memory access mode back to what it was.
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default_mem_access
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}
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# Capture the mode of a given reset so that we can use it later in the
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# reset-assert handler.
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proc init_reset { mode } {
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global _RESETMODE
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set _RESETMODE $mode
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if {[using_jtag]} {
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jtag arp_init-reset
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}
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}
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